采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术,制备出应变Si/弛豫Si0.9Ge01/渐变组分弛豫SiGe/Si衬底.通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺,有效地降低了表面粗糙度和位错密度.与Ge组分突变相比,采用线性渐变组分后,应变硅材料表面粗糙度从3.07nm减小到0.75nm,位错密度约为5×104 cm-2,表面应变硅层应变度约为0.45%.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术,制备出应变Si/弛豫Si0.9Ge01/渐变组分弛豫SiGe/Si衬底.通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺,有效地降低了表面粗糙度和位错密度.与Ge组分突变相比,采用线性渐变组分后,应变硅材料表面粗糙度从3.07nm减小到0.75nm,位错密度约为5×104 cm-2,表面应变硅层应变度约为0.45%.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术，制备出应变Si/弛豫Si0.9Ge0.1/渐变组分弛豫SiGe/Si衬底. 通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺，有效地降低了表面粗糙度和位错密度.与Ge组分突变相比，采用线性渐变组分后，应变硅材料表面粗糙度从3.07nm减小到0.75nm，位错密度约为5E4cm-2，表面应变硅层应变度约为0.45%.     

应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

一种适合制作CMOS的SiGe PMOSFET

在通常适合于制作埋沟SiGe NMOSFET的Si/弛豫SiGe/应变Si/弛豫SiGe缓冲层/渐变Ge组分层的结构上,制作成功了SiGe PMOSFET.这种SiGe PMOSFET将更容易与SiGe NMOSFET集成,用于实现SiGe CMOS.实验测得这种结构的SiGe PMOSFET在栅压为3.5V时最大饱和跨导比用作对照的Si PMOS提高约2倍,而与常规的应变SiGe沟道的器件相当.     

纳米CMOS电路的应变Si衬底制备技术

应变硅衬底材料——弛豫SiGe层作为应变硅技术应用的基础,其质量的好坏对应变硅器件性能有致命的影响。综述了近年来用于纳米CMOS电路的各类弛豫SiGe层的制备技术,并对弛豫SiGe层中应变测量技术进行了简单的介绍,以期推动应变硅技术在我国芯片业的应用。     

基于SiGe虚拟衬底的低场迁移率提升140%的应变Si沟道NMOS器件 Cui Wei(崔伟)1,2,Tang Zhaohuan(唐昭焕)2, Tan Kaizhou(谭开洲)2, Zhang Jing(张静)2,

本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。     

Ge/SiGe异质结构肖特基源漏MOSFET

制备了氧化铪(HfO2)高k介质栅Si基Ge/SiGe异质结构肖特基源漏场效应晶体管(SB-MOSFET)器件,研究了n型掺杂Si0.16Ge0.84层对器件特性的影响,分析了n型掺杂SiGe层降低器件关态电流的机理。使用UHV CVD沉积系统,采用低温Ge缓冲层技术进行了材料生长,首先在Si衬底上外延Ge缓冲层,随后生长32 nm Si0.16Ge0.84和12 nm Ge,并生长1 nm Si作为钝化层。使用原子力显微镜和X射线衍射对材料形貌和晶体质量进行表征,在源漏区沉积Ni薄膜并退火形成NiGe/Ge肖特基结,制备的p型沟道肖特基源漏MOSFET,其未掺杂Ge/SiGe异质结构MOSFET器件的空穴有效迁移率比相同工艺条件制备的硅器件的高1.5倍,比传统硅器件空穴有效迁移率提高了80%,掺杂器件的空穴有效迁移率与传统硅器件的相当。     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET’s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor （p-MOSFET） is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si （LT-Si）/10nm S i buffer was grown by Molecular Beam Epitaxy （MBE）, in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET＇s （L=4.2μm） transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm^2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.     

Electron mobility enhancement in strained-Si n-MOSFETs fabricatedon SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si_1-xGe_x-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si_0.75Ge_0.26 and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si_1-xGe_x layer     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

Band offset induced threshold variation in strained-Si nMOSFETs

Due to the offset in the valence band, strained-Si nMOSFETs exhibit a -100 mV threshold shift and 4% degradation of the subthreshold slope per each 10% increase of Ge content in the relaxed SiGe layer. The correlation between the threshold shift and strained layer thickness is investigated based on device simulations. In a certain range of the strained-Si layer thickness, the threshold and subthreshold slope change gradually, posing a concern of larger device parameter variation. A larger threshold distribution is observed in devices fabricated with a strained layer thickness comparable to the depletion depth.     

Hole transport in UTB MOSFETs in strained-Si directly on insulator with strained-Si thickness less than 5 nm

Hole transport is studied in ultrathin body (UTB) MOSFETs in strained-Si directly on insulator (SSDOI) with a Si thickness down to 1.4 nm. In these Ge-free SSDOI substrates, the Si is strained in biaxial tension with strain levels equivalent to strained-Si on relaxed SiGe, with Ge contents of 30 and 40% Ge. The hole mobility in SSDOI decreases slowly for Si thicknesses above 4 nm, but drops rapidly below that thickness. Relative to silicon-on-insulator control devices of equal thickness, SSDOI displays significant hole mobility enhancement for Si film thicknesses above 3.5 nm. Peak hole mobility is improved by 25% for 40% SSDOI relative to 30% SSDOI fabricated by the same method, demonstrating the benefits of strain engineering for 3.1-nm-thick UTB MOSFETs.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462