IP protection of DSP algorithms for system on chip implementation

Silicon technology has now advanced to the point that there is a serious mismatch in the time taken to design advanced silicon-based systems and the time to market for any new product or product derivative. To obviate this delay, a new paradigm is emerging based on intellectual property (IP) exchange, where designers and differing companies share subsystems (virtual cores) between themselves to reduce design time to acceptable levels. To this end, over 150 companies including all the major players formed the Virtual Socket Interface Alliance in March 1997. The protection of IP has become a serious issue as intercompany subsystem design exchange becomes more commonplace. This paper presents new techniques to protect the IP of virtual cores that implement digital signal processing (DSP) algorithms. The approach involves embedding codewords into the design of fundamental signal processing algorithms such as digital filters and the DFT in such a way that proof of authorship can be retained, and, if required, easily identified. The techniques discussed can be adapted to protect other fundamental DSP algorithms such as convolution and correlation. The protection of IP via watermarking techniques is increasingly being applied at all levels of design. It is particularly advantageous if such techniques are applied at the highest abstraction levels in the design flow, and if such techniques are applied at basic algorithm level, they become very difficult to detect at lower levels of system design     

实时H.263+视频编码器的DSP实现

在多媒体处理芯片TM-1300的开发平台上,快速实现了H.263 视频编码器。首先,根据H.263 编码算法要求,介绍TM-1300适合视频通信开发的特点及其开发环境;然后,将编码算法移植到TM-1300平台并进行大量的优化,其中,重点讨论了位移估值的优化算法。由实验结果可知,使用本文给出的优化算法,可以在TM-1300上快速实现H.263 编码器,满足视频实时编解码的要求,且已应用于实际视频通信产品中。     

Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling

In this paper, we present a general approach which specifically targets reduction of redundant computation in common digital-signal processing (DSP) tasks such as filtering and matrix multiplication. We show that such tasks can be expressed as multiplication of vectors by scalars and this allows fast multiplication by sharing computation. Vector scaling operation is decomposed to find the most effective precomputations which yield a fast multiplier implementation. Two decomposition approaches are presented, one based on a greedy decomposition and the other based on fixed-size lookup and this leads to two multiplier architectures for vector-scalar products. Analog simulation of an example multiplier shows a speed advantage by a factor of about 1.85 over a conventional carry save array multiplier. Further simulations using 0.18 /spl mu/ technology show up to 20% speed advantage over Booth encoded Wallace tree multipliers.     

DSP implementation of real-time MPEG-2 audio decoder using novelsynthesis filter bank

An efficient synthesis filter is presented which can carry out real-time MPEG-2 audio decoding. The proposed algorithm reduces the number of MAC operations by adopting novel IDCT and windowing schemes, exploiting a multichannel structure, and implementing CGD techniques. The DSP implementation is MPEG-2 compliant and achieves real-time processing with 60% reduction in run-time compared with a fast ISO decoder     

Parallel implementation for iterative image restoration algorithms on a parallel DSP machine

Many low-level image processing algorithms which are posed as variational problems can be numerically solved using local and iterative relaxation algorithms. Because of the structure of these algorithms, processing time will decrease nearly linearly with the addition of processing nodes working in parallel on the problem. In this article, we discuss the implementation of a particular application from this class of algorithms on the 8×8 processing array of the AT&T Pixel system. In particular, a case study for a image interpolation algorithm is presented. The performance of the implementation is evaluated in terms of the absolute processing time. We show that near linear speedup is achieved for such iterative image processing algorithms when the processing array is relatively small.This work was made possible by a grant from the AT&T University Equipment Program.     

车载FSK信号的实时高精度检测与DSP实现

本文基于16位定点运算精度的TMS320C50 DSP芯片,提出了一种通过频谱分析实现时高精度检测FSK信号的方法,并从理论上对主要技术给予了详细的论述,文章最后给出了具体硬件实现及部分实验结果。     

基于颜色查找空间的自然感彩色融合算法及DSP实时实现

基于颜色查找空间的自然感彩色融合算法是一种快速有效地将自然光参考图像的色调"着色"到多波段融合图像的方法。颜色查找空间针对不同环境和场景的人眼观察任务,寻求参考图像与多波段融合图像的像素点灰度坐标索引与颜色值的最佳匹配关系,为融合图像提供类似于自然光参考图像并适合于解读场景的色彩,缩短处理时间,应用前景广泛。针对颜色查找表的实时视频帧处理任务,需要特定的硬件和软件设计,满足对于算法环境适应性和实时处理效果的需求。选用了TI公司的32位定点处理器TMS320DM642采集PAL制模拟视频,实时彩色融合,在标准显示器上输出PAL制彩色融合视频。文中介绍了基于颜色查找空间的自然感彩色融合算法的处理流程,DSP实时处理的硬件和软件设计,实现二维颜色查找表实时处理采用的优化方法,以及在未来适于颜色查找表算法的硬件、系统和应用推广。     

Multiprocessor DSP with multistage switching network for videocoding

A dynamic load balancing method is proposed that uses a multistage switching network to solve the problem of load concentration on certain processors for video coding in multiprocessor digital signal processors. (DSPs) This method balances the processing load by distributing the total load among the processor elements having smaller loads. The load distribution is performed by the multistage switching network, which transmits the load quantity information within the network. A scheduling method for a motion picture coding algorithm using multiprocessor DSPs is also proposed. This scheduling method takes full advantage of the multistage switching network functions when distributing the processing load and sorting the processed results. By using computer simulation, multiprocessor DSP performance with the proposed method is shown to be double that of a conventional multiprocessor DSP when an initially unbalanced load is allocated to the processors, as in picture coding for TV conferences     

多处理器DSP:为媒体处理器带来一股清风

DSP的流媒体领域是个新涌现的热门,包括三大类:带宽/连接应用,语音/数据/图像/视频应用,WAN上的多媒体(MOW,Multimedia Over WAN),这块市场的增长速度高达22%,2007年预计可达到360亿美元.     

Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidanceof over-constrained synchronization, and its simplified clocking requirements.However, analysis and optimization of self-timed systems under real-time constraintsis challenging due to the complex, irregular dynamics of self-timed operation.In this paper, we review a number of high-level intermediate representationsfor compiling dataflow programs onto self-timed DSP platforms, including representationsfor modeling the placement of interprocessor communication (IPC) operations;separating synchronization from data transfer during IPC; modeling and optimizinglinear orderings of communication operations; performing accurate design spaceexploration under communication resource contention; and exploring alternativeprocessor assignments during the synthesis process. We review the structureof these representations, and discuss efficient techniques that operate onthem to streamline scheduling, communication synthesis, and power managementof multiprocessor DSP implementations.     

Design,implementation, and evaluation of learning algorithms for dynamic real-time network monitoring

Network monitoring is necessary so as to ensure high reliability and availability in telecom networks. One of the main challenges posed by state-of-the-art monitoring tools is the creation of network baselines. Such baselines include thresholds that can be used to determine whether monitored values (with a given context, e.g., time) represent normal network operation or not. The size and complexity of current (and future) networks make it infeasible to manually determine and set baselines for each network operator and metric, let alone adapting the thresholds to changes in network conditions. This leads to the use of default baselines and/or setting baselines only once and never changing them throughout the lifetime of network elements. This does not only cause inefficient operation but could have implications for network reliability and availability. In this paper, we present the design, implementation, and evaluation of DARN: a collection of analytics and machine learning-based algorithms aimed at ensuring that network baselines are automatically adapted to different metric evolution. DARN has been comprehensively evaluated on a deployment with real traffic to confirm accuracy of generated baselines, a 22% improvement in accuracy due to baseline adaptation and a 72% reduction in false alarms.     

基于多媒体DSP TM1300的运动估计算法研究及实现

提出一种用于H.263视频编码的快速运动估计的算法——NDA，通过PC仿真后将它移植到多媒体DSP TM1300上，并对它进行了改进和优化。实际运行的测试结果表明，NDA的性能要优于TMN3．0给出的运动估计算法，接近FS。文中还给出了衡量实际运动估计算法性能的测试方法。     

数字调制信号开环解调的DSP实现

随着微电子技术和计算技术的发展，尤其是DSP处理速度的提高，解调器的全数字化实现已成为现实。重点讨论了软件无线电中数字调制信号解调的DSP实现方案。     

Resource-constrained loop list scheduler for DSP algorithms

We present a new algorithm for resource-constrained scheduling for digital signal processing (DSP) applications when the number of processors is fixed and the objective is to obtain a schedule with the minimum iteration period. This type of scheduling is best suited for moderate speed applications where conservation of area and power is more important than speed. We define and make use of newgraph dependent constraints to obtain a lower bound estimate on the iteration period for any data-flow graph. By satisfying these constraints before performing the scheduling task, we can restrict the design space and can generate valid schedules in less time than previously reported. The graph dependent constraints provide a more accurate lower bound estimate on the iteration period than previously published results. This new scheduling algorithm exploits the iterative nature of DSP algorithms and uses aniterative-loop based scheduling approach. This resource scheduling algorithm has been incorporated in the Minnesota ARchitecture Synthesis (MARS) system. Our approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining to generate optimal and near optimal schedules.This research was supported by the Advanced Research Projects Agency under grant number F33615-93-C-1309 and the office of Naval Research under contract number N00014-91-J-1008.     

光OFDM实时处理的研究

阐述了光OFDM实时处理方法的优势,介绍了一种光OFDM实时处理器的硬件构成,包括接收和发射端机的模数采样器(ADC)与FPGA处理芯片的选取.研究了光OFDM实时处理中的信道均衡机制和MIMO算法,实现光OFDM处理芯片在光OFDM实时传输系统中的应用.     

DSP指令集仿真器的设计与实现

介绍几种常用的仿真器的设计方案,通过比较分析各自原理的优缺点,结合硬件性能,设计了基于ZWFcore的指令集仿真器ZWISS。通过对其CPU、多级存储单元、陷阱、内存管理单元（MMU）、存储保护系统（MPS）以及物理内存属性（PMA）的仿真,较完善地完成对ZWFcore的仿真。为DSP硬件评估、DSP算法实现提供了良好的软件模拟平台。     

基于DSP的FQPSK/CEFQPSK调制器实现

首先介绍了适用于深空通信的费赫尔正交移相键控（FQPSK）调制技术。为了改善其包络起伏特性,又介绍了一种严格的恒包络调制技术——恒包络正交移相键控（CEFQPSK）,它不但保持了FQPSK较高的带宽效率、无干扰和抖动的优点,而且实现了严格的恒包络,能够将发射机射频功率放大器效率发挥到最大。最后采用了一系列简化运算的处理方法,在TI公司的DSP中实现了这2种调制,达到信号高速输出的目的。     

基于DSP开发系统设计与实现

为了设计一个性能稳定的DSP开发系统,利用TI公司最新推出的TMS320F28335作为微处理器,该芯片为32位浮点型DSP。在采用浮点DSP设计系统时,不需要考虑处理的动态范围和精度,比定点DSP在软件编写方面更容易,更适合采用高级语言编程。外围电路主要包含电源电路、RAM扩展电路、晶振电路和复位电路,用来辅助DSP的工作。利用电源管理芯片设计电源电路,可以有效解决其他型号的DSP对上电顺序的要求;扩展的外部RAM可以使程序的调试与下载更加方便。利用外部时钟源作为时钟输入,使其输入时钟更加稳定的同时,也可为具有相同时钟的多个DSP使用。利用三端监控芯片来实现系统的手动复位和自动复位,使系统的稳定性大大提高。     

虹膜识别算法的研究及实现

Daugman提出的虹膜识别算法具有准确性高，速度快的，但是有关该算法的具体实现却未见文献报道。对Daugman的算法进行了研究，工尝试该算法的实现，提出了一种新的粗定位和精定位相结合的算法来快速位虹膜。在滤波过程中仅利用了实部滤波器就可减少代码长度，而不影响识别效果，其中包括图像的预处理，多尺度2D Gabor滤波器的构造，虹膜码及Hamming距离的计算等。实验结果表明，该方法计算速度快，提取特征的效果好，可用于实际的身份鉴别系统。