采用砷化镓场效应晶体管的18千兆赫前置放大器

引言砷化镓金属半导体场效应晶体管(MESFET)比双极晶体管噪声低,增益高,适用于高至20千兆赫左右频率下的低噪声前置放大器。金属半导体场效应晶体管的特性金属半导体场效应晶体管由高阻衬底上的薄导电层构成。N 型导电层包括源和漏两个欧姆接触以及栅的整流接触。图1示出的砷化镓金属半导体场效应晶体管中,1×200微米的栅     

基于沟道及电极修饰的酞菁铜场效应晶体管的性能提高研究

利用对四联苯p -4P 以及五氧化二钒V2O5同时修饰导电沟道及源/漏电极,大幅 提高了基于酞菁铜CuPc场效应晶体管的性能。本文通过在绝缘层SiO2和有源层CuPc 之间插入p-4p缓冲薄层,同时在源/漏电极Al与有机半导体之间引入电极修饰层V2O5, 使得CuPc场效应晶体管的饱和迁移率和电流开/关比分别提高到5×10-2cm2 / V s和 104。p -4P能够诱导p型CuPc形成高度取向的连续薄膜,使得载流子能够在有源层中 更好地传输;而V2O5能够调节载流子的注入势垒,并可有效地降低沟道接触电阻(Rc)。 此方法能够在降低器件制备成本的前提下,大幅提高器件的性能。     

具有短沟道的结栅场效应晶体管的特性

本文推导出具有短沟道长度的结栅场效应晶体管的两段模型。在此模型中,导电沟道分为源段和漏段。在源段假设包含有热电子效应修正项的渐变沟道近似。对于漏段,用公式阐述了和过剩载流子堆积效应有关的饱和速度传输。给出了归一化设计曲线和两个样品器件的特性。     

栅长为1.5微米延迟时间为50微微秒的高速GaAsFET逻辑器件

对于GaAs场效应晶体管来说,虽然栅长为1.5微米是够长的了,但仍能试制出电路延迟时间为50微微秒(功耗为5.7毫瓦/门)的GaAs场效应晶体管逻辑集成电路。与硅栅MOS场效应晶体管的制造方法相同,是以栅金属作掩蔽,用离子注入方法形成n~ 的漏区和源区。由于该n~ 层的横向扩散,不使栅金属和n~ 层不致电气短路,然后进行深离子注入,使表面载流子浓度稍微降低些。     

超薄势垒InAlN/GaN HFET器件高频特性分析

采用二次外延重掺杂n+ GaN实现非合金欧姆接触,并通过优化干法刻蚀和金属有机化学气相沉积(MOCVD)外延工艺,有效降低了欧姆接触电阻.将非合金欧姆接触工艺应用于InAlN/GaN异质结场效应晶体管(HFET)器件制备,器件的有效源漏间距缩小至600 nm.同时,结合40 nm T型栅工艺,制备了高电流截止频率(fT)和最大振荡频率(fmax)的InAlN/GaN HFET器件.结果显示减小欧姆接触电阻和栅长后,器件的电学特性,尤其是射频特性得到大幅提升.栅偏压为0V时,器件最大漏源饱和电流密度达到1.88 A/mm;直流峰值跨导达到681 mS/mm.根据射频小信号测试结果外推得到器件的fT和fmax同为217 GHz.     

基于Pd/SWNT/Al结构的场效应晶体管的研究

碳纳米管因具有良好的物理机械性能而得到广泛的研究,其最重要的应用之一是构建场效应晶体管(FET).文章提出并研究了一种非对称接触的单壁碳纳米管场效应晶体管(SWNT-FET),并对其电学特性进行了表征.在该器件中,SWNT被作为FET的沟道,两种不同功函数的金属被用来与SWNT形成肖特基接触;SWNT一端与低功函数金属Al形成源极,另一端与高功函数金属Pd形成漏极.该类器件可应用于下一代纳米集成电路中.     

场效应晶体管中接触孔应力技术的研究

随着集成电路集成度的不断提高以及场效应晶体管尺寸的微缩,沟道载流子迁移率退化越来越严重,通过沟道应力技术提升载流子迁移率从而提高性能的技术被广泛应用。介绍了接触孔应力对沟道的影响,分析了接触孔与沟道间距离及源漏区外延厚度对沟道应力的影响。通过对应力传导机制的分析,提出了通过调节侧墙材料和结构来优化沟道应力的方法。     

fT为350 GHz的InAlN/GaN HFET高频器件研究

采用再生长n+ GaN非合金欧姆接触工艺研制了具有高电流增益截止频率(fT)的InAlN/GaN异质结场效应晶体管 (HFETs),器件尺寸得到有效缩小,源漏间距减小至600 nm.通过优化干法刻蚀和n+ GaN外延工艺,欧姆接触总电阻值达到0.16 Ω·mm,该值为目前金属有机化学气相沉积(MOCVD)方法制备的最低值.采用自对准电子束曝光工艺实现34 nm直栅.器件尺寸的缩小以及欧姆接触的改善,器件电学特性,尤其是射频特性得到大幅提升.器件的开态电阻(Ron)仅为0.41 Ω·mm,栅压1 V下,漏源饱和电流达到2.14 A/mm.此外,器件的电流增益截止频率(fT)达到350 GHz,该值为目前GaN基HFET器件国内报道最高值.     

氧化锌纳米线晶体管的电学特性研究

成功制作了氧化锌纳米线沟道场效应晶体管器件,所制作器件的电学性能通过I-V测试进行了分析。使用了水浴法生长了单晶性完整的氧化锌纳米线,该纳米线被用作背栅场效应晶体管的沟道,采用光刻方式制备的器件具有良好的直流特性,进行退火后进一步改善器件的源漏接触,提高器件性能,最终制备成功的场效应晶体管显示出p型MOS的特性,其开关态电流比达到105。在Vds=2.5 V时,跨导峰值为0.4μS,栅氧电容约为0.9 fF,器件夹断电压Vth为0.6 V,沟道迁移率约为87.1 cm2/V.s,计算得到氧化锌纳米线载流子浓度ne=6.8×108 cm-3。在Vgs=0 V时,器件沟道电阻率为100Ω.cm。     

f_T为350 GHz的InAlN/GaN HFET高频器件研究（英文）

采用再生长n~+GaN非合金欧姆接触工艺研制了具有高电流增益截止频率(f_T)的InAlN/GaN异质结场效应晶体管(HFETs),器件尺寸得到有效缩小,源漏间距减小至600 nm.通过优化干法刻蚀和n~+GaN外延工艺,欧姆接触总电阻值达到0.16Ω·mm,该值为目前金属有机化学气相沉积(MOCVD)方法制备的最低值.采用自对准电子束曝光工艺实现34 nm直栅.器件尺寸的缩小以及欧姆接触的改善,器件电学特性,尤其是射频特性得到大幅提升.器件的开态电阻(R_(on))仅为0.41Ω·mm,栅压1 V下,漏源饱和电流达到2.14 A/mm.此外,器件的电流增益截止频率(f_T)达到350 GHz,该值为目前GaN基HFET器件国内报道最高值.     

基于插入WO3缓冲层并五苯有机场效应晶体管性能的研究

The pentacene-based organic field effect transistor （OFET） with a thin transition metal oxide （WO3） layer between pentacene and metal （AI） source/drain electrodes was fabricated. Compared with conventional OFET with only metal AI source/drain electrodes, the introduction of the WO3 buffer layer leads to the device performance enhancement. The effective field-effect mobility and threshold voltage are improved to 1.90 em2/（V.s） and 13 V, respectively. The performance improvements are attributed to the decrease of the interface energy barrier and the contact resistance. The results indicate that it is an effective approach to improve the OFET performance by using a WO3 buffer layer.     

Accurate Extraction of Schottky Barrier Height and Universality of Fermi Level De-Pinning of van der Waals Contacts

Due to Fermi level pinning (FLP), metal-semiconductor contact interfaces result in a Schottky barrier height (SBH), which is usually difficult to tune. This makes it challenging to efficiently inject both electrons and holes using the same metal—an essential requirement for several applications, including light-emitting devices and complementary logic. Interestingly, modulating the SBH in the Schottky–Mott limit of de-pinned van der Waals (vdW) contacts becomes possible. However, accurate extraction of the SBH is essential to exploit such contacts to their full potential. In this study a simple technique is proposed to accurately estimate the SBH at the vdW contact interfaces by circumventing several ambiguities associated with SBH extraction. Using this technique on several vdW contacts, including metallic 2H-TaSe₂, semi-metallic graphene, and degenerately doped semiconducting SnSe₂, it is demonstrated that vdW contacts exhibit a universal de-pinned nature. Superior ambipolar carrier injection properties of vdW contacts are demonstrated (with Au contact as a reference) in two applications, namely, a) pulsed electroluminescence from monolayer WS₂ using few-layer graphene (FLG) contact, and b) efficient carrier injection to WS₂ and WSe₂ channels in both n-type and p-type field effect transistor modes using 2H-TaSe₂ contact.     

Fabrication of asymmetric Ge Schottky tunneling source n-channel field-effect transistor and its characterization of tunneling conduction

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short channel effect and to reduce the off-state current. An obstacle to implement a STS FET with a high mobility Ge channel was to form a metal/Ge contact with a low electron barrier height (Φ_BN). Recently, we succeeded in the fabrication of a TiN/Ge contact with an extremely low Φ_BN. In this study, a Ge-STS n-channel FET was fabricated, here PtGe/Ge and TiN/Ge contacts were used as the source and the drain. The device showed well-behaved transistor operation. From the current-voltage measurements in the wide temperature range of 160–300 K, the conduction mechanism from the source to the channel is confirmed to be field emission tunneling. This result will be the first step toward achieving a high-performance Ge-STS n-FET.     

Carrier Type Control of WSe2 Field‐Effect Transistors by Thickness Modulation and MoO3 Layer Doping

Control of the carrier type in 2D materials is critical for realizing complementary logic computation. Carrier type control in WSe₂ field‐effect transistors (FETs) is presented via thickness engineering and solid‐state oxide doping, which are compatible with state‐of‐the‐art integrated circuit (IC) processing. It is found that the carrier type of WSe₂ FETs evolves with its thickness, namely, p‐type (<4 nm), ambipolar (≈6 nm), and n‐type (>15 nm). This layer‐dependent carrier type can be understood as a result of drastic change of the band edge of WSe₂ as a function of the thickness and their band offsets to the metal contacts. The strong carrier type tuning by solid‐state oxide doping is also demonstrated, in which ambipolar characteristics of WSe₂ FETs are converted into pure p‐type, and the field‐effect hole mobility is enhanced by two orders of magnitude. The studies not only provide IC‐compatible processing method to control the carrier type in 2D semiconductor, but also enable to build functional devices, such as, a tunable diode formed with an asymmetrical‐thick WSe₂ flake for fast photodetectors.     

Analysis of contact effects in fully printed p-channel organic thin film transistors

Contact effects have been analyzed in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source–drain contacts. In these devices, contact effects lead to an apparent decrease of the field effect mobility with decreasing L and to a failure of the gradual channel approximation (GCA) in reproducing the output characteristics. Experimental data have been reproduced by two-dimensional numerical simulations that included a Schottky barrier (Φ_b = 0.46 eV) at both source and drain contacts and the effects of field-induced barrier lowering. The barrier lowering was found to be controlled by the Schottky effect for an electric field E < 10⁵ V/cm, while for higher electric fields we found a stronger barrier lowering presumably due to other field-enhanced mechanisms. The analysis of numerical simulation results showed that three different operating regimes of the device can be identified: (1) low |V_ds|, where the channel and the Schottky diodes at both source and drain behave as gate voltage dependent resistors and the partition between channel resistance and contact resistance depends upon the gate bias; (2) intermediate V_ds, where the device characteristics are dominated by the reverse biased diode at the source contact, and (3) high |V_ds|, where pinch-off of the channel occurs at the drain end and the transistor takes control of the current. We show that these three regimes are a general feature of the device characteristics when Schottky source and drain contacts are present, and therefore the same analysis could be extended to TFTs with different semiconductor active layers.     

Temperature behavior and modeling of ohmic contacts to Si implanted n-type GaN

The behavior of an ohmic contact to an implanted Si GaN n-well in the temperature range of 25-300 °C has been investigated. This is the sort of contact one would expect in many GaN based devices such as (source/drain) in a metal-oxide-semiconductor transistor. A low resistivity ohmic contact was achieved using the metal combination of Ti (350 Å)/Al (1150 Å) on a protected (SiO₂ cap) and unprotected samples during the post implantation annealing. Sheet resistance of the implanted layer and metal-semiconductor contact resistance to N⁺ GaN have been extracted at different temperatures. Both, the experimental sheet resistance and the contact resistance decrease with the temperature and their characteristics are fitted by means of physical based models.     

Electric Field Tunable Interlayer Relaxation Process and Interlayer Coupling in WSe2/Graphene Heterostructures

Transition metal dichalcogenides van der Waals (vdWs) heterostructures present fascinating optical and electronic phenomena, and bear tremendous significance for electronic and optoelectronic applications. As the significant merits in vdWs heterostructures, the interlayer relaxation of excitons and interlayer coupling at the heterointerface reflect the dynamic behavior of charge transfer and the coupled electronic/structural characteristics, respectively, which may give rise to new physics induced by quantum coupling. In this work, upon tuning the photoluminescence (PL) properties of WSe₂/graphene and WSe₂/MoS₂/graphene heterostructures by virtue of electric field, it is demonstrated that the interlayer relaxation of excitons at the heterointerface in WSe₂/graphene, which is even stronger than that in MoS₂/graphene and WSe₂/MoS₂ , plays a dominant role in PL tuning in WSe₂/graphene, while the carrier population in WSe₂ induced by electric field has a minor contribution. In addition, it is discovered that the interlayer coupling between monolayer WSe₂ and graphene is enhanced under high electric field, which breaks the momentum conservation of first order Raman‐allowed phonons in graphene, yielding the enhanced Raman scattering of defects in graphene. The interplay between electric field and vdWs heterostructures may provide versatile approaches to tune the intrinsic electronic and optical properties of the heterostructures.     

Lateral WSe2 Homojunction through Metal Contact Doping: Excellent Self-powered Photovoltaic Photodetector

Here an IR-heating chemical vapor deposition (CVD) approach enabling fast 2D-growth of WSe₂ thin films is reported, and the great potential of metal contact doping in building CVD-grown WSe₂-based lateral homojunction is demonstrated by contacting with TiN/Ni metals in favor of holes/electrons injection. Shortening nanosheet channel to ≈2 µm leads to pronounced enhancement in the performance of diode. The fabricated WSe₂-based diode exhibits high rectification ratios without the need of gate modulation and can work efficiently as photovoltaic cell, with maximum open circuit voltage reaching up to 620 mV and a high power conversion efficiency over 15%, empowering it as superb self-powered photodetector for visible to near-infrared lights, with photoresponsivity over 0.5 A W⁻¹ and a fast photoresponse speed of 10 µs under 520 nm illumination. It is of practical significance to achieve well-performed photovoltaic devices with CVD-grown WSe₂ using fab-friendly metals and simple processing, which will help pave the way toward future mass production of optoelectronic chips.     

A silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide for high output-power density

We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide (LB-SOI MESFET) and its maximum output power density (P_max). To optimize the surface electric field and improve the breakdown voltage, we eliminated part of the oxide and replaced it with n-type silicon. By creating an n⁺–n region on the source side and modifying the electric field distribution, the breakdown voltage improved by 42% compared to a conventional device. Channel control is realized by varying the depletion layer width underneath the metal gate contact. This modulates the thickness of the conducting channel and thus controls the current between the source and the drain. Continuation of the n-type silicon on top of the buried oxide after the gate metal changes the depletion layer and increases the total channel charge for conduction, so the drain current increases by a factor of five compared to a conventional SOI MESFET. In addition, P_max is increased by a factor of 17.7 with respect to a conventional structure, which is important for large-signal analog applications. Consequently, our novel LB-SOI MESFET has superior electrical characteristics.     

Pt/Al stacked metals gate MESFET

A new InP MESFET structure both with a gate structure of stacked metal and with a active channel of stacked layer is proposed. The gate metals are constituted by a double metal structure, Pt/Al. It improves the barrier height and reduces the reverse leakage current in the MFSFET. This is due to the formation of Al₂O₃, and becoming a Pt/Al/Al₂O₃/InP, metal-insulating-semiconductor structure in the gate region of the transistor. The conductive channel is constituted by a stack-layered structure, a n-InP layer and an i-InP layer. A transfer characteristics of excellent pitch off, and transconductance of 93 mS/mm is derived. It also shows a negative differential resistance effect on the MESFET. The illumination and temperature effect of the transistor are brought into discussed.