Manufacturability of 20-nm ultrathin body fully depleted SOI devices with FUSI metal gates

Ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) devices show great performance due to undoped channels and excellent electrostatic control. Very high drive currents and good off-state leakage, ideal subthreshold slope, and small drain-induced barrier lowering (DIBL) have been reported with devices as short as 20 nm. The ultrathin channel enables high device performance, but it imposes a new set of problems. The control of the silicon thickness has become the dominant source of device variations. Selective epitaxial growth has become a necessity to achieve high performance and reliable contacts to UTB FDSOI devices. This work discusses silicon thickness control, selective epitaxial growth, and the mid-gap gate module needed for fully depleted devices. Very good control of short channel effect is shown and drive current fluctuations are discussed.     

Low-power high-performance double-gate fully depleted SOI circuitdesign

Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance. We study how the added back-gate capacitance affects circuit power and performance; how to tradeoff the enhanced short-channel effect immunity with the added back-channel leakage; and how the coupling between the front- and back-gates affects circuit reliability. Our analyses over different technology generations using the MEDICI device simulator show that DGFD SOI circuits have significant advantages in driving high output load. DGFD SOI circuits also show excellent ability in controlling leakage current. However, for low output load, no gain is obtained for DGFD SOI circuits. Also, it is necessary to optimize the back-gate oxide thickness for best leakage control. Moreover, threshold variation may cause reliability problems for thin back-gate oxide DGFD SOI circuits operated at low supply voltage     

Modeling of ultrathin double-gate nMOS/SOI transistors

An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poisson's equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures     

Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs

A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.     

Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs

In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T/sub SI/) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T/sub SI/ fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T/sub SI/ fluctuation scattering are remarkably enhanced with reducing T/sub SI/, so that they could help explain the experimental mobility behavior.     

Enhancement of charge storage performance in double-gate silicon nanocrystal memories with ultrathin body structure

We propose double-gate silicon nanocrystal memories (NCMs) with ultrathin body structure. Double-gate NCMs experimentally show larger threshold voltage shift (/spl Delta/V/sub th/) and longer charge retention time than single-gate NCMs. These superior behaviors in double-gate NCMs are explained by the increase in the body potential due to electrons in one side nanocrystals that prevent electrons in the other side nanocrystals from escaping. Thinner transistor body enhances the mutual influence between electrons in both sides. It is also found that the endurance characteristics are also improved by the reduced potential difference in the tunnel oxide.     

Characteristics of double-gate SOI CMOS nanotransistors for promising technologies with a low power consumption level

A procedure, allowing one to optimize topological and electrophysical parameters of double gate SOI nanotransistors with a thin unalloyed working area, with underlap gate and drain/source regions with regard to the physical restrictions and process requirements, without recourse to the 2D-simulation, is considered. Based on the numerical simulation results, the selection criteria of the key topological parameters of transistors for implementing the requirements in accordance with the International Technology Roadmap for Semiconductor 2010 Edition program for promising applications with a low power consumption level are discussed. The complex analysis of the VACs of transistors and gate characteristics, such as a time switching delay, as well as active and static power, shows that prototypes of the considered units are applicable for implementing high-performance VLSI projects.     

A comparison of floating-body potential in H-gate ultrathin gate oxide partially depleted SOI pMOS and nMOS devices based on 90-nm SOI CMOS process

Based on a 90-nm silicon-on-insulator (SOI) CMOS process, the floating-body potential of H-gate partially depleted SOI pMOS and nMOS devices with physical gate oxide of 14 /spl Aring/ is compared. For pMOS devices, because the conduction-band electron (ECB) tunneling barrier is lower (/spl cong/3.1 eV), the ECB direct-tunneling current from the n/sup +/ poly-gate beside the body terminal will contribute to a large amount of electron charges into the neutral region and dominate the floating-body potential under normal operations. Conversely, owing to the higher valence-band hole tunneling barrier (/spl cong/4.5 eV), the floating-body potential of nMOS devices is dominated by the band-to-band-tunneling mechanism at the drain-body junction, not the direct-tunneling mechanism.     

Mobility-field behavior of fully depleted SOI MOSFET's

This work reports measured effective mobility vs. effective vertical electric field and the accompanying experimental method of extraction for the fully depleted (FD) SOI MOSFET. The effective channel mobility vs. effective vertical electric field behavior was investigated as a function of the SOI film doping concentration, the SOI back-gate bias, and the SOI film thickness. The validity of using the approximation, Q_i=C_ox(V_GS-V_TH), for the inversion charge density in FD SOI is examined and experimentally confirmed     

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.     

面向SOI波导-单模光纤耦合的硅微透镜设计

硅光集成的优势在高速光电子领域不断凸显,被广泛应用于各种通信场景中。在硅基集成技术发展过程中,其面临的一个典型技术难点是硅波导与单模光纤的耦合。本文设计了波导边缘集成的硅微透镜结构,经BPM法(Beam Propagation Method)计算验证该结构可实现3μm厚SOI波导与纤芯直径86μm单模光纤90的近场耦合效率,具备高集成度、高耦合效率、多场景适用等优点。     

An analytical model for fully depleted single gate SOI MOS transistors including lattice temperature effects

An analytical model for fully depleted SOI MOSFETs is presented. Major small geometry effects such as carrier velocity saturation, mobility degradation, channel length modulation, and drain induced barrier lowering are included. Device self heating due to low thermal conductivity of a buried oxide layer is included in carrier mobility modelling. Thermal effects are also included in threshold voltage expression. Source, drain, and channel resistance effects are also included. Modelled results are then compared to available measured data and are shown to be in very good agreement.     

Analysis of conduction in fully depleted SOI MOSFETs

The conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed. In these devices the ideal inverse subthreshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitances. For above-threshold conduction, with decreasing silicon film thickness the inversion charges penetrate more deeply into the film and the transconductance increases because of the decreasing fraction of surface conduction     

High-temperature and self-heating effects in fully depleted SOI MOSFETs

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600 °K by using the SILVACO¹ TCAD tools. In particular, we have studied their current-voltage characteristics (I_D-V_GS and I_D-V_DS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.     

Heating mechanisms of LDMOS and LIGBT in ultrathin SOI

Temperature rises due to self-heating in silicon-on-insulator (SOI) power devices may lead to performance degradation and reliability problems. This letter investigates the mechanisms and spatial distribution of heat generation in linearly graded SOI LDMOS and LIGBT devices. While Joule heating dominates in LDMOS devices, hole collection at the p-well-drift region junction contributes strongly to the heating of LIGBT's. Also, the presence of both Joule and recombination heating makes the heating profile more uniform in LIGBT's. These effects combine to yield a temperature rise in LIGBT's that is more uniform and lower on average than that in LDMOS devices     

Observation of mobility enhancement in ultrathin SOI MOSFETs

The mobility in n-channel SOI MOSFETs exhibits a significant increase as the SOI film becomes thinner than 1000 Å. At a 500 Å SOI thickness, the mobility values are distributed in the 700-1100 cm²/Vs range, which are obviously higher than the value in a bulk MOSFET having an identical doping concentration. The observed mobility enhancement has been explained by a decrease in the vertical electric field, associated with the complete depletion of the SOI film     

中子辐照单晶硅与激光退火制备SOI结构的研究

SOI材料在制作高速、抗辐照电路、复合功能器件以及实现三维集成电路等方面有着重要的应用前景.实现SOI结构有多种途径:除蓝宝石外延(SOS)工艺外,还有多晶硅的激光或电子束熔化再结晶、石墨条加热再结晶和在单晶硅中大剂量深注入氧形成隔离层等方法.利用中子辐照使单晶硅损伤,得到了绝缘层衬底,然后以激光退火消除表面层损     

Analysis of hot-electron reliability and device performance in80-nm double-gate SOI n-MOSFET's

In this paper, we employ a comprehensive Monte Carlo-based simulation method to model hot-electron injection, to predict induced device degradation, and to simulate and compare the performance of two double-gate fully depleted silicon-on-insulator n-MOSFET's (one with a lightly-doped channel and one with a heavily-doped channel) and a similar lightly-doped single-gate design. All three designs have an effective channel length of 80 nm and a silicon layer thickness of 25 mm. Monte Carlo simulations predict a spatial retardation between the locations of peak hot-electron injection into the front and back oxides. Since the observed shift is a significant portion of the channel length, the retardation effect greatly influences induced degradation in otherwise well-designed SOI devices. This effect may signal an important consideration for sub-100-nm design strategy. Simulations were also conducted to compare transistor performance against a key figure of merit. Evaluation of reliability and performance results indicate that the double-gate design with a lightly doped channel offers the best tradeoff in immunity to hot-electron-induced degradation and performance     

On the transient operation of partially depleted SOI NMOSFET's

The transient operation of partially depleted (PD) Silicon-On-Insulator (SOI) NMOSFET's is investigated, based on two-dimensional numerical simulations. The studied devices have a gate length of 0.2 μm and a floating body. They are designed for a supply voltage of 2 V. In the case of gate transient, we show that the body voltage is more influenced by the capacitive coupling with the gate electrode than the impact ionization current. Further, we demonstrate, for the first time, that the anomalous subthreshold slope, that exists in a DC static transfer I-V curve, does not exist in fast transient mode because the minimum time constant for body charging by impact ionization current is on the order of 3 ns in such devices     

Computer-aided performance assessment of fully depleted SOI CMOSVLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies