Low-Temperature Polymer-Based Three-Dimensional Silicon Integration

We describe a low-temperature polymer-based 3D integration technique for wafer-scale transplantation of micrometer thick circuit and device layers onto another host wafer. The maximum temperature of this approach is 340 ^oC. It incorporates a low-k semiconductor compatible dielectric bonding media, employs tools that are readily available within a fabrication environment, and is very simple to implement. Another unique characteristic of the approach is the simultaneous separation of the transplanting layer from the donor assembly with the bonding to the host assembly. Alignment registration of several micrometers between device layers is demonstrated. Electrical results of 3D inverter circuit along with demonstration of four-device-layer 3D integrated stack are presented.     

A Tunable RF MEMS Inductor on Silicon Incorporating an Amorphous Silicon Bimorph in a Low-Temperature Process

A novel tunable radio frequency microelectromechanical system inductor based on the bimorph effect of an amorphous silicon (a-Si) and aluminum structural layer is presented. The outer turns of the inductor have a vertical height of 450 mum when no voltage is applied. A 32% tuning range with high inductance (5.6-8.2 nH) is achieved by the application of a voltage, with the structure completely flattening at 2 V. With no actuation, the peak quality factor is 15, and the self-resonance frequency is 7 GHz. The fact that the device is fabricated on Si in a low-temperature (150 degC) process enhances the potential for system integration     

A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

We proposed here a reliability model that successfully introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.      

Low-Temperature Epitaxy of Compressively Strained Silicon Directly on Silicon Substrates

We report epitaxial growth of compressively strained silicon directly on (100) silicon substrates by plasma-enhanced chemical vapor deposition. The silicon epitaxy was performed in a silane and hydrogen gas mixture at temperatures as low as 150°C. We investigate the effect of hydrogen dilution during the silicon epitaxy on the strain level by high-resolution x-ray diffraction. Additionally, triple-axis x-ray reciprocal-space mapping of the samples indicates that (i) the epitaxial layers are fully strained and (ii) the strain is graded. Secondary-ion mass spectrometry depth profiling reveals the correlation between the strain gradient and the hydrogen concentration profile within the epitaxial layers. Furthermore, heavily phosphorus-doped layers with an electrically active doping concentration of ~2 × 10²⁰ cm⁻³ were obtained at such low growth temperatures.     

Low-Temperature Bonding of Laser Diode Chips on Silicon Substrates Using Plasma Activation of Au Films

A low-temperature bonding of vertical-cavity surface-emitting laser (VCSEL) chips on Si substrates was achieved by using plasma activation of Au films. After the surfaces of Au films were cleaned using an Ar radio frequency plasma, bonding was carried out by contact in ambient air with applied static pressure. The experimental results showed that surface morphological change (the reduction of asperity width) as well as removal of adsorbed organic contaminants by plasma treatment significantly improved the quality of joints. At a bonding temperature of 100degC, the die-shear strength exceeded the failure criteria of MIL-STD-883.     

N型背发射极晶体硅太阳电池模拟研究

N型晶体太阳电池由于少子寿命高、光致衰减低、弱光响应好等优点,近年来在高效率低成本太阳电池领域一直备受关注。利用PC1D模拟,对N型背发射极晶体硅太阳电池进行了分析。结果表明,背发射极掺杂浓度、结深、背表面复合速率、前表面掺杂浓度及复合速率都对电池转换效率有较大影响,尤其是电池前表面与背表面复合速率对电池性能的影响最为明显,而电池前表面场掺杂深度则对电池性能影响较小。对于前表面复合来说,当前表面复合速率小于1×103cm/s时,电池性能受表面复合速率变化的影响很小;但复合速率超过1×103cm/s后,电池转换效率快速下降。背表面复合对电池效率影响则更明显,当背表面复合速率超过1×104cm/s后,电池转换效率急剧下降,在背表面复合速率增大到1×106cm/s时,电池效率下降到不足5%,而在电池背表面复合速度较小时(10~103cm/s)则可获得较高的转换效率。     

一种低信噪比下雷达辐射源识别方法

针对低信噪比下雷达辐射源信号分类,首先提出了基于高阶累积量和小波包变换相结合的特征提取方法,然后设计支持向量机分类器,并运用粒子群优化算法对分类器的参数进行寻优,最终实现对雷达辐射源信号的自动分类。仿真实验结果表明,在信噪比为-4dB时,6种雷达辐射源信号的平均识别率仍能达到93.83%,在低信噪比环境下取得了较为理想的分类效果。     

双注入多晶硅发射极高性能BiCMOS技术研究

研究了一种ＢｉＣＭＯＳ新技术，基区和发射区均通过发射极多晶注入，使形成的基区更浅，更窄；通过等平面氧化形成的鸟嘴，将版图设计中３．０μｍ，的发射极条宽“挤”为２．０μｍ左右。提高了器件性能。在器件结构及工艺设计中，中能提高工艺的兼容性，简化工艺。     

77K多晶硅发射区双极型晶体管

本文介绍了适于77K工作的多晶硅发射区双极型晶体管,给出了在不同工作电流条件下的电流增益的温度模型。结果表明在小电流条件下电流增益随温度下降而下降得更为剧烈,并且讨论了在不同注入情况下,浅能级杂质的陷阱作用对截止频率的影响。     

新型红外硅微电流光电池的研制

利用ＰＮ结的光生伏特效应,采用集成电路的工艺技术和特殊处理方法,研制成功了短路电流大于１０μＡ,开路电压大于８Ｖ的红外硅微电流光电池。     

Low-Temperature Polycrystalline Silicon Thin-Film Flash Memory With Hafnium Silicate

In this paper, we have successfully fabricated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type poly-Si-thin-film transistor (TFT) memories employing hafnium silicate as the trapping layer with low-thermal budget processing (les600degC). It was demonstrated that the fabricated memories exhibited good performance in terms of relatively large memory window, high program/erase speed (1 ms/10 ms), long retention time (>10⁶ s for 20% charge loss), and 2-bit operation. Interestingly, we found that these memories depicted very unique disturbance behaviors, which are obviously distinct from those observed in the conventional SONOS-type Flash memories. We thought these specific characteristics are closely related to the presence of the inherent defects along the grain boundaries. Therefore, the elimination of the traps along the grain boundaries in the channel is an important factor for achieving high performance of the SONOS-type poly-Si-TFT Flash memory     

A Low-Temperature Pressureless Bonding Process Using a Trimodal Mixture System of Ag Nanoparticles

A low-temperature pressureless bonding process using a mixture of trimodal-sized Ag nanoparticles was proposed to form excellent Cu-to-Cu joints. Cu-to-Cu joints formed using the mixed Ag nanoparticles at 350°C for 5 min showed bonding strength of 13.7 MPa, in spite of the bonding process without pressure. Elongated dimples observed on the fracture surface of the Cu-to-Cu joint strongly support the effect of the trimodal mixture system of Ag nanoparticles in the low-temperature pressureless bonding process.     

Performance of a Self-Aligned InP/GaInAs SHBT with a Novel T-Shaped Emitter

研究了一种采用新的T型发射极技术的自对准InP/GaInAs单异质结双极晶体管.采用了U型发射极图形结构、选择性湿法腐蚀、LEU以及空气桥等技术,成功制作了U型发射极尺寸为2μm×12μm的器件.该器件的共射直流增益达到170,残余电压约为0.2V,膝点电压仅为0.5V,而击穿电压超过了2V.器件的截止频率达到85GHz,最大振荡频率为72GHz,这些特性使此类器件更适合于低压、低功耗及高频方面的应用.     

基于脉冲样本图的雷达辐射源识别新技术

现代雷达信号体制越来越复杂,使得现有的雷达信号特征描述方式很难有效地对复杂体制辐射源进行描述分析。为解决复杂体制雷达辐射源的识别问题,文章提出了一种新的雷达信号描述方式——脉冲样本图,并设计了一种可以对其进行分类识别的BP(Back Propagation)网络。仿真实验表明该网络可以对脉冲样本图进行有效识别,为解决复杂体制雷达辐射源的识别提供了新思路。     

Integrated Ambient Light Sensor With Nanocrystalline Silicon on a Low-Temperature Polysilicon Display Panel

A novel integrated ambient light sensor using nanocrystalline silicon fabricated using low-temperature polysilicon technology has been developed on a display panel. The photosensing structure of the silicon nanocrystals embedded in a dielectric film sandwiched between the bottom metal and top indium-thin-oxide electrodes perfectly eliminates backlight noise, which is a problem typical of conventional p-i-n photodiodes integrated into a liquid-crystal display. Experimental results indicate that the Si-nanocrystal photosensor has better performances in dark current and quantum efficiency than those of the p-i-n diode. The Si-nanocrystal photosensor also exhibited response linearity and speed comparable to the p-i-n diode. In terms of long-term operation and reliability, the lifetime of the Si-nanocrystal photosensor is roughly two orders longer than that of the p-i-n diode. The Si-nanocrystal ambient light sensor has considerable flexibility in the design of spectrum, geometry, and the readout circuit, which is achieved by adjusting the nanocrystal size and applying a vertical stacking structure. The Si-nanocrystal photosensor can be a promising low-cost PMOS-only solution for various photosensing applications on display panels.      

A Low-Noise X-Band Parametric Amplifier Using a Silicon Mesa Diode

This paper summarizes a cooperative effort to develop silicon mesa variable-capacitance diodes and to evaluate their potential for achieving low-noise amplification in the high microwave frequency range. Cutoff frequencies of about 70 kMc at zero-bias voltage (corresponding to 140 kMc at maximum reverse bias voltage) with a total permissible voltage swing in excess of 5 volts have been obtained. A versatile degenerate X-band parametric amplifier was developed which, when used in conjunction with these silicon mesa diodes, achieved a radiometer noise temperature of 130°K at 8.5 kMc with a 50-Mc bandwidth at 17-db gain. The measured performance of the diode (figure of merit) is compared with the first-order theory in an operating radar system. The over-all performance of the amplifier improved the observed system sensitivity by 6 db.     

A Novel Five-Photo-Mask Low-Temperature Polycrystalline-Silicon CMOS Structure With Improved Contact Resistance

In this letter, a novel five-mask low-temperature polycrystalline-silicon (LTPS) complementary metal–oxide–semiconductor (CMOS) structure was proposed to improve cost competitiveness of CMOS products on the market and was verified by manufacturing test samples using the five-mask LTPS CMOS process. Selective contact-barrier-metal formation process was first introduced to solve the high-contact-resistance problem encountered between indium–tin-oxide and doped poly-Si source/drain. The five-mask CMOS devices showed comparable device performances to CMOS devices with conventional structure, i.e., 1.32 V of threshold voltage and 267.6 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ of maximum field-effect mobility for NMOS, and those of $-$1.24 V and 125.2 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ for PMOS, respectively.