多晶硅膜及其薄发射极退火特性的研究

本文详细研究了退火方式和条件对多晶硅膜结构、电性能以及多晶硅接触薄发射极的发射极电阻的影响。结果表明，１０００℃以上热退火对于减小发射极电阻、降低多晶硅膜的电阻率有利；激光退火不但能减小发射极电阻，导致更低的多晶硅膜电阻率，而且还能获得极浅的单晶发射结，在改善薄发射极晶闸管特性方面显示出较大优势。     

Incorporation of dielectric layers into the processing of III-nitride-based heterostructure field-effect transistors

Dielectric layers within III-nitride transistor technology can act either as passivation layers or as gate-dielectric layers. In this paper, we reflect on both issues and present novel approaches of dielectric schemes. In both cases, the elimination of surface traps or, more generally, of surface states is a key issue in obtaining improved device performance. As gate dielectrics, we introduced and investigated thermally and photoelectrochemically generated Al_xGa_2−xO₃, SiO₂, the combination of Al_xGa_2−xO₃ and SiO₂ (tandem-dielectric stack), and e-beam-deposited Al₂O₃. These dielectric layers serve simultaneously as a passivation layer. In addition, we introduced plasma-enhanced chemical-vapor deposition (PECVD)-deposited SiN_x for passivation. The results highlight the importance of passivation and the introduction of gate dielectrics and emphasize the relationship between surface states and improved direct-current (DC) performance. Backed by additional measurements, we proposed a different gateleakage mechanism for heterostructure field-effect transistor (HFET) and metal-oxide semiconductor heterostructure field-effect transistor (MOSHFET) devices.     

The algorithm for the piezoresistance coefficients of p-type polysilicon

In order to improve the piezoresistance theory of polysilicon, based on the tunneling piezoresistance model, using the mechanisms of approximate valence band equation and shifts of the hole transfer and hole conduction mass by stress, a novel algorithm for the piezoresistance coefficients of p-type polysilicon is presented. It proposes three fundamental piezoresistance coefficients π₁₁, π₁₂ and π₄₄ of the grain neutral and grain boundary regions, separately. With those piezoresistance coefficients, the gauge factors of the p-type polysilicon nanofilm and the p-type common polysilicon film are calculated, and then the plots of the gauge factor as a function of doping concentration are given, which are consistent with the experimental results.     

退火温度对PZT薄膜电容器性能的影响

通过简单的溶胶–凝胶法和快速热处理工艺,获得了在Pt/Ti/SiO2/Si基片上生长良好的PZT薄膜。制膜工艺简单,不需要回流和高温去结晶水,即可获得(111)择优取向的PZT薄膜。PZT薄膜经快速热处理在550~650℃退火,薄膜致密和平滑,均具有良好的铁电和介电特性,其最佳退火温度为600℃。     

Analysis of rapid thermal annealings of boron and arsenic in polysilicon emitter structures

The codiffusion of implanted boron and arsenic during rapid thermal annealing in a polysilicon/monocrystalline silicon system used for high speed bipolar integrated circuit technology has been investigated. Such a process allows a uniformly high concentration in the emitter regions. It induces a very shallow emitter-base junction depth for an n-p-n transistor. On the contrary, in p-n-p configuration, when the arsenic dose is lower than the boron dose, boron deeply penetrates the single-crystal silicon, causing problems for fabricating shallow junctions. The rapid thermal annealing-induced redistribution of arsenic and boron implanted at various implant doses in a 380 nm low-pressure chemical vapor deposition (LPCVD) polysilicon layer has been studied by secondary ion mass spectroscopy measurements. A strong lowering of the minority dopant diffusion in the polysilicon film is observed due to the high concentration of the other dopant. This effect is mainly related to grain boundary trap saturation while the electric field issued from dopant activation in the fastly recrystallized amorphous layer due to arsenic implantation in the upper region of the LPCVD film has a lesser effect. Transmission electron microscopy measurements show that recrystallization extends deeper than the amorphous layer, which is responsible for the increase of grain size. Sheet resistance measurements have been performed as an approach to the electrical behavior for these structures.     

Stress and resistivity controls on in situ boron doped LPCVD polysilicon films for high-Q MEMS applications

addition, polysilicon thin films ported approaches avoid the high temperature annealing process (> 1000 ℃), and the promising properties of these films make them suitable for high-Q and high-f MEMS devices.     

应力和电阻率可控的适用于高品质因子MEMS器件的原位掺硼LPCVD多晶硅薄膜

The simultaneous control of residual stress and resistivity of polysilicon thin films by adjusting the deposition parameters and annealing conditions is studied. In situ boron doped polysilicon thin films deposited at 520 ℃ by low pressure chemical vapor deposition （LPCVD） are amorphous with relatively large compressive residual stress and high resistivity. Annealing the amorphous films in a temperature range of 600-800 ℃ gives polysilicon films nearly zero-stress and relatively low resistivity. The low residual stress and low resistivity make the polysilicon films attractive for potential applications in micro-electro-mechanical-systems （MEMS） devices, especially in high resonance frequency （high-f） and high quality factor （high-Q） MEMS resonators. In addition, polysilicon thin films deposited at 570 ℃ and those without the post annealing process have low resistivities of 2-5 mΩ·cm. These reported approaches avoid the high temperature annealing process （〉 1000 ℃）, and the promising properties of these films make them suitable for high-Q and high-f MEMS devices.     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

Investigation of the polysilicon p-i-n diode and diode string as a process compatible and portable ESD protection device

正The polysilicon p-i-n diode displays noticeable process compatibility and portability in advanced technologies as an electrostatic-discharge(ESD) protection device.This paper presents the reverse breakdown,current leakage and capacitance characteristics of fabricated polysilicon p-i-n diodes.To evaluate the ESD robustness,the forward and reverse TLPⅠ-Ⅴcharacteristics were measured.The polysilicon p-i-n diode string was also investigated to further reduce capacitance and fulfill the requirements of tunable cut-in or reverse breakdown voltage. Finally,to explain the effects of the device parameters,we analyze and discuss the inherent properties of polysilicon p-i-n diodes.     

氧退火对钛酸锶钡薄膜介电常数的影响

采用氩离子束镀膜技术和硅平面工艺,在SiO2/Si衬底上淀积钛酸锶钡 (Ba1-xSrxTiO3)薄膜,研究在氧气氛中不同温度和时间的退火对薄膜的介电常数的影响。实验结果表明,在退火温度为600℃时,随着氧退火时间的增加,钛酸锶钡薄膜的相对介电常数减小;而在退火时间为30 min时,随着退火温度的增加,钛酸锶钡薄膜的相对介电常数增加。微观结构分析和极化理论解释了这一现象。     

SOI-CMOS devices on beam-recrystallized polysilicon

Control of the grain boundary direction in the recrystallized polycrystalline silicon (polysilicon) island is achieved by the direction of the laser scanning. By using this technique, the source-to-drain short in a short-channel MOSFET is almost eliminated, and MOSFETs with channel lengths of 2–3 μm level in both n-channel and p-channel mode are fabricated with a good uniformity and reproducibility.The low-field electron and hole mobilities are 580 cm²/Vsec and 220 cm²/Vsec, respectively.19-stage CMOS ring oscillators with nominal channel lengths of 3μm are fabricated. The minimum propagation delay is 280 psec/stage at a supply voltage of 10 V, and the minimum power delay product is 0.13 pJ/stage.     

光纤损耗对零色散波长附近传输的暗孤子脉冲的影响

利用一种解析的方法研究有损耗的光纤零色散波长附近传输的光脉冲,在正常色散区,得到了稳定的暗孤子解析解,并由此讨论了存在小损耗时暗孤子的形成条件,以及小损耗对暗孤子的中心位置,相位,振幅,频率等参数的影响。     

Field emission characteristics of an oxidized porous polysilicon field emitter using the electrochemical oxidation process

The field emission characteristics of an oxidized porous polysilicon (OPPS) were investigated with Pt/Ti multilayer electrode using the electrochemical oxidation (ECO) process. A Pt/Ti multilayer electrode, using ECO, showed highly efficient and stable electron emission characteristics; moreover, it can be applied to large area of a glass substrate with a low temperature process. Electron emission characteristics were improved with O₂ annealing at 600 °C after the ECO process. It was found that forming a high quality oxide layer from the ECO-formed SiO₂ was crucial in improving electron emission characteristics. The Pt/Ti OPPS field emitter, which was annealed at 600 °C for 5 h, showed an efficiency of 3.81% at      

激光制备高介CaTiO3-CaTiSiO5高频介质陶瓷

采用激光烧结技术成功制备致密、高介电常数的CaTiO3-CaTiSiO5高频介质陶瓷。使用X射线衍射仪、扫描电子显微镜分析样品的晶相组成和显微组织,利用精密阻抗分析仪测试陶瓷样品的介电性能。结果表明,激光烧结CaTiO3-CaTiSiO5介质陶瓷致密、介电常数（εr=376）高达固相烧结样品的5倍,这应归因于激光烧结C...     

The influence of silicon heat treatments on the minority carrier generation and the dielectric breakdown in MOS structures

The minority carrier lifetime of Si and the dielectric breakdown of SiO₂ on Si has been investigated as a function of various high temperature treatments preceding the formation of the SiO₂ layer. Annealing wafers in H₂ or certain H₂ -containing ambients prior to oxidation lea to a dramatic decrease in the number of breakdown defects found in capacitors. The higher the temperature the more effective is the defect removal. Using this process the defect density could be reproducibly controlled at ≤10 defects/cm , and in some cases wafers with no defects were found. The defects appear to be related to some airborn contamination and can be increased by exposure to air and to certain aqueous cleaning steps. By “soaking≓ the Si wafers in an equilibrium gas mixture containing SiH₄ as well as HCl, it was possible to prevent etching of the Si but yet expose the wafer to approximately 4% HC1 for longer times and at higher temperatures, 12 75‡C, than is possible with the well known HCl-oxidation process. It was found that this treatment will remove Au, Fe, and Cu from intentionally contaminated wafers but at rates much slower than would be expected from bulk-diffusion, rate-limited transport. Soaking at 1275‡C led to minority carrier lifetimes comparable but not significantly better than for HCl-oxidized wafers.     

超高压BCD工艺中多晶硅电阻的可靠性分析及实现

多晶硅电阻由于其独特的温度特性及电迁移效应,阻值受温度和电流的影响很大,针对应用于超高压BCD工艺中的多晶硅电阻,其可靠性需进行特别分析和设计。通过对0.18μm 700 V BCD工艺中不同掺杂浓度多晶硅电阻的测试与分析,结合多晶硅结构、导电机制、焦耳热效应及电迁移理论,分析了焦耳热和电迁移对多晶硅电阻的影响,并实现了高压BCD工艺中高可靠性的多晶硅电阻。     

CCD多晶硅层间复合绝缘介质研究

电荷耦合器件(CCD)多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响。将氮化硅和二氧化硅作为CCD多晶硅层间复合绝缘介质,采用扫描电子显微镜(SEM)和电学测试系统研究了多晶硅层间氮化硅和二氧化硅复合绝缘介质对CCD多晶硅栅间距和多晶硅层间击穿电压的影响。研究结果表明,多晶硅层间复合绝缘介质中的氮化硅填充了多晶硅热氧化层的微小空隙,可以明显改善绝缘介质质量。多晶硅层间击穿电压随着氮化硅厚度的增加而增大,但太厚的氮化硅会导致CCD暗电流明显增大。由于复合绝缘介质质量好,可以减小CCD多晶硅的氧化厚度。     

Mechanical integrity of polysilicon films exposed to hydrofluoric acid solutions

This paper presents the results from a comparative study of Young’s modulus, residual stress, and membrane burst pressure of undoped LPCVD polysilicon films exposed to various concentrations of hydrofluoric acid (HF). Load deflection measurements on square membranes of polysilicon with residual tensile stress were used to obtain estimates of Young’s modulus, residual stress and burst pressure. The polysilicon membranes were exposed to four different solutions of the 49% by weight reagent HF including 10:1 DI water and HF, 1:1 DI water the HF, commercial 10:1 buffered oxide etchant, or pure HF (i.e. 49% by weight reagent). Two control groups were studied composed of membranes with no treatment and membranes exposed to DI water. Young’s modulus changed from an average of 190 GPa for the control groups to an average of 240 GPa for films exposed to pure HF. Residual stress values exhibited a less pronounced and opposite change, with an average of 42 MPa for the control groups and an average of 27 MPa for films exposed to pure HF. Similarly, burst pressure was seen to decrease with increasing HF concentration, ranging in value from an average of 96.5 kPa (14 psi) for the control groups to an average of 34.5 kPa (5 psi) for films exposed to pure HF. It was found that the change in the investigated mechanical properties of polysilicon was approximately equal for HF:DI solutions of HF concentration above 10%. Furthermore, for solutions of equal HF concentration, the addition of the buffering agent decreases the effect on membrane burst pressures significantly.     

CCD栅介质工艺对多晶硅层间介质的影响

CCD多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响.采用扫描电子显微镜和电学测试系统研究了CCD栅介质工艺对多晶硅层间介质的影响.研究结果表明:栅介质工艺对多晶硅层间介质形貌具有显著的影响.栅介质氮化硅淀积后进行氧化,随着氧化时间延长,靠近栅介质氮化硅区域的多晶硅层间介质层厚度增大.增加氮化硅氧化时间到320 min,多晶硅层间薄弱区氧化层厚度增加到227 nm.在前一次多晶硅氧化后淀积一层15 nm厚氮化硅,能够很好地填充多晶硅层间介质空隙区,不会对CCD工作电压产生不利的影响.     

FCCL高频介电性能和介电热系数的测量

由于FCCL机械性能特点,FCCL大量用于刚挠结合电路。而应用在FCCL电路的传输频率较低,高频介电性能如介电常数Dk和介电损耗角正切Df未被重视起来。本文利用分离式介质谐振腔法测量FCCL的介电性能,测试频率范围为1.1 GHz~15.5 GHz,并测量其介电常数热系数TCEr。