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1.
本文详细研究了退火方式和条件对多晶硅膜结构、电性能以及多晶硅接触薄发射极的发射极电阻的影响。结果表明,1000℃以上热退火对于减小发射极电阻、降低多晶硅膜的电阻率有利;激光退火不但能减小发射极电阻,导致更低的多晶硅膜电阻率,而且还能获得极浅的单晶发射结,在改善薄发射极晶闸管特性方面显示出较大优势。 相似文献
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D. Mistele T. Rotter A. Horn O. Katz Z. Bougrioua J. Aderhold J. Graul G. Bahir J. Salzman 《Journal of Electronic Materials》2003,32(5):355-363
Dielectric layers within III-nitride transistor technology can act either as passivation layers or as gate-dielectric layers.
In this paper, we reflect on both issues and present novel approaches of dielectric schemes. In both cases, the elimination
of surface traps or, more generally, of surface states is a key issue in obtaining improved device performance. As gate dielectrics,
we introduced and investigated thermally and photoelectrochemically generated AlxGa2−xO3, SiO2, the combination of AlxGa2−xO3 and SiO2 (tandem-dielectric stack), and e-beam-deposited Al2O3. These dielectric layers serve simultaneously as a passivation layer. In addition, we introduced plasma-enhanced chemical-vapor
deposition (PECVD)-deposited SiNx for passivation. The results highlight the importance of passivation and the introduction of gate dielectrics and emphasize
the relationship between surface states and improved direct-current (DC) performance. Backed by additional measurements, we
proposed a different gateleakage mechanism for heterostructure field-effect transistor (HFET) and metal-oxide semiconductor
heterostructure field-effect transistor (MOSHFET) devices. 相似文献
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In order to improve the piezoresistance theory of polysilicon, based on the tunneling piezoresistance model, using the mechanisms of approximate valence band equation and shifts of the hole transfer and hole conduction mass by stress, a novel algorithm for the piezoresistance coefficients of p-type polysilicon is presented. It proposes three fundamental piezoresistance coefficients π11, π12 and π44 of the grain neutral and grain boundary regions, separately. With those piezoresistance coefficients, the gauge factors of the p-type polysilicon nanofilm and the p-type common polysilicon film are calculated, and then the plots of the gauge factor as a function of doping concentration are given, which are consistent with the experimental results. 相似文献
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C. Gontrand A. Merabet S. Krieger-Kaddour C. Dubois J. P. Vallard 《Journal of Electronic Materials》1993,22(1):135-141
The codiffusion of implanted boron and arsenic during rapid thermal annealing in a polysilicon/monocrystalline silicon system
used for high speed bipolar integrated circuit technology has been investigated. Such a process allows a uniformly high concentration
in the emitter regions. It induces a very shallow emitter-base junction depth for an n-p-n transistor. On the contrary, in
p-n-p configuration, when the arsenic dose is lower than the boron dose, boron deeply penetrates the single-crystal silicon,
causing problems for fabricating shallow junctions. The rapid thermal annealing-induced redistribution of arsenic and boron
implanted at various implant doses in a 380 nm low-pressure chemical vapor deposition (LPCVD) polysilicon layer has been studied
by secondary ion mass spectroscopy measurements. A strong lowering of the minority dopant diffusion in the polysilicon film
is observed due to the high concentration of the other dopant. This effect is mainly related to grain boundary trap saturation
while the electric field issued from dopant activation in the fastly recrystallized amorphous layer due to arsenic implantation
in the upper region of the LPCVD film has a lesser effect. Transmission electron microscopy measurements show that recrystallization
extends deeper than the amorphous layer, which is responsible for the increase of grain size. Sheet resistance measurements
have been performed as an approach to the electrical behavior for these structures. 相似文献
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addition, polysilicon thin films ported approaches avoid the high temperature annealing process (> 1000 ℃), and the promising properties of these films make them suitable for high-Q and high-f MEMS devices. 相似文献
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The simultaneous control of residual stress and resistivity of polysilicon thin films by adjusting the deposition parameters and annealing conditions is studied. In situ boron doped polysilicon thin films deposited at 520 ℃ by low pressure chemical vapor deposition (LPCVD) are amorphous with relatively large compressive residual stress and high resistivity. Annealing the amorphous films in a temperature range of 600-800 ℃ gives polysilicon films nearly zero-stress and relatively low resistivity. The low residual stress and low resistivity make the polysilicon films attractive for potential applications in micro-electro-mechanical-systems (MEMS) devices, especially in high resonance frequency (high-f) and high quality factor (high-Q) MEMS resonators. In addition, polysilicon thin films deposited at 570 ℃ and those without the post annealing process have low resistivities of 2-5 mΩ·cm. These reported approaches avoid the high temperature annealing process (〉 1000 ℃), and the promising properties of these films make them suitable for high-Q and high-f MEMS devices. 相似文献
8.
HfTiO氮化退火对MOS器件电特性的影响 总被引:1,自引:0,他引:1
采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。 相似文献
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正The polysilicon p-i-n diode displays noticeable process compatibility and portability in advanced technologies as an electrostatic-discharge(ESD) protection device.This paper presents the reverse breakdown,current leakage and capacitance characteristics of fabricated polysilicon p-i-n diodes.To evaluate the ESD robustness,the forward and reverse TLPⅠ-Ⅴcharacteristics were measured.The polysilicon p-i-n diode string was also investigated to further reduce capacitance and fulfill the requirements of tunable cut-in or reverse breakdown voltage. Finally,to explain the effects of the device parameters,we analyze and discuss the inherent properties of polysilicon p-i-n diodes. 相似文献
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Control of the grain boundary direction in the recrystallized polycrystalline silicon (polysilicon) island is achieved by the direction of the laser scanning. By using this technique, the source-to-drain short in a short-channel MOSFET is almost eliminated, and MOSFETs with channel lengths of 2–3 μm level in both n-channel and p-channel mode are fabricated with a good uniformity and reproducibility.The low-field electron and hole mobilities are 580 cm2/Vsec and 220 cm2/Vsec, respectively.19-stage CMOS ring oscillators with nominal channel lengths of 3μm are fabricated. The minimum propagation delay is 280 psec/stage at a supply voltage of 10 V, and the minimum power delay product is 0.13 pJ/stage. 相似文献
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The field emission characteristics of an oxidized porous polysilicon (OPPS) were investigated with Pt/Ti multilayer electrode using the electrochemical oxidation (ECO) process. A Pt/Ti multilayer electrode, using ECO, showed highly efficient and stable electron emission characteristics; moreover, it can be applied to large area of a glass substrate with a low temperature process. Electron emission characteristics were improved with O2 annealing at 600 °C after the ECO process. It was found that forming a high quality oxide layer from the ECO-formed SiO2 was crucial in improving electron emission characteristics. The Pt/Ti OPPS field emitter, which was annealed at 600 °C for 5 h, showed an efficiency of 3.81% at 相似文献
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The minority carrier lifetime of Si and the dielectric breakdown of SiO2 on Si has been investigated as a function of various high temperature treatments preceding the formation of the SiO2 layer.
Annealing wafers in H2 or certain H2 -containing ambients prior to oxidation lea to a dramatic decrease in the number of breakdown defects found in capacitors.
The higher the temperature the more effective is the defect removal. Using this process the defect density could be reproducibly
controlled at ≤10 defects/cm , and in some cases wafers with no defects were found. The defects appear to be related to some
airborn contamination and can be increased by exposure to air and to certain aqueous cleaning steps.
By “soaking≓ the Si wafers in an equilibrium gas mixture containing SiH4 as well as HCl, it was possible to prevent etching of the Si but yet expose the wafer to approximately 4% HC1 for longer
times and at higher temperatures, 12 75‡C, than is possible with the well known HCl-oxidation process. It was found that this
treatment will remove Au, Fe, and Cu from intentionally contaminated wafers but at rates much slower than would be expected
from bulk-diffusion, rate-limited transport. Soaking at 1275‡C led to minority carrier lifetimes comparable but not significantly
better than for HCl-oxidized wafers. 相似文献
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电荷耦合器件(CCD)多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响。将氮化硅和二氧化硅作为CCD多晶硅层间复合绝缘介质,采用扫描电子显微镜(SEM)和电学测试系统研究了多晶硅层间氮化硅和二氧化硅复合绝缘介质对CCD多晶硅栅间距和多晶硅层间击穿电压的影响。研究结果表明,多晶硅层间复合绝缘介质中的氮化硅填充了多晶硅热氧化层的微小空隙,可以明显改善绝缘介质质量。多晶硅层间击穿电压随着氮化硅厚度的增加而增大,但太厚的氮化硅会导致CCD暗电流明显增大。由于复合绝缘介质质量好,可以减小CCD多晶硅的氧化厚度。 相似文献
18.
James A. Walker Kaigham J. Gabriel Mehran Mehregany 《Journal of Electronic Materials》1991,20(9):665-670
This paper presents the results from a comparative study of Young’s modulus, residual stress, and membrane burst pressure
of undoped LPCVD polysilicon films exposed to various concentrations of hydrofluoric acid (HF). Load deflection measurements
on square membranes of polysilicon with residual tensile stress were used to obtain estimates of Young’s modulus, residual
stress and burst pressure. The polysilicon membranes were exposed to four different solutions of the 49% by weight reagent
HF including 10:1 DI water and HF, 1:1 DI water the HF, commercial 10:1 buffered oxide etchant, or pure HF (i.e. 49% by weight reagent). Two control groups were studied composed of membranes with no treatment and membranes exposed to
DI water. Young’s modulus changed from an average of 190 GPa for the control groups to an average of 240 GPa for films exposed
to pure HF. Residual stress values exhibited a less pronounced and opposite change, with an average of 42 MPa for the control
groups and an average of 27 MPa for films exposed to pure HF. Similarly, burst pressure was seen to decrease with increasing
HF concentration, ranging in value from an average of 96.5 kPa (14 psi) for the control groups to an average of 34.5 kPa (5
psi) for films exposed to pure HF. It was found that the change in the investigated mechanical properties of polysilicon was
approximately equal for HF:DI solutions of HF concentration above 10%. Furthermore, for solutions of equal HF concentration,
the addition of the buffering agent decreases the effect on membrane burst pressures significantly. 相似文献
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CCD多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响.采用扫描电子显微镜和电学测试系统研究了CCD栅介质工艺对多晶硅层间介质的影响.研究结果表明:栅介质工艺对多晶硅层间介质形貌具有显著的影响.栅介质氮化硅淀积后进行氧化,随着氧化时间延长,靠近栅介质氮化硅区域的多晶硅层间介质层厚度增大.增加氮化硅氧化时间到320 min,多晶硅层间薄弱区氧化层厚度增加到227 nm.在前一次多晶硅氧化后淀积一层15 nm厚氮化硅,能够很好地填充多晶硅层间介质空隙区,不会对CCD工作电压产生不利的影响. 相似文献