A 54-MHz CMOS programmable video signal processor for HDTVapplications

A 54-MHz CMOS video processor with a systolic architecture suited for two-dimensional symmetric FIR (finite impulse response) filtering is reported. The circuit is a one-dimensional digital filter comprising a control part and an array of eight multiplication-accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2-μm CMOS technology, and it dissipates less than 500 mW at a 54-MHz clock frequency     

A high-performance custom standard-cell CMOS equalizer for telecommunications applications

A high-performance CMOS programmable amplitude equalizer has been implemented with a dynamic range greater than 100 dB and supply rejection greater than 60 dB at 1 kHz from both supplies. This was accomplished using a balanced architecture. A nonreturn-to-zero sample-and-hold circuit is proposed that is also parasitic-insensitive. The circuits are implemented using a standard-cell methodology.     

A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.     

A field programmable analog array for CMOS continuous-time OTA-Cfilter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade     

Low-voltage CMOS programmable gain amplifier for UHF applications

A CMOS programmable gain amplifier suitable for low-voltage operation over the very high frequency range is presented. The scheme is based on a very simple common-mode feedforward pseudo-differential pair with resistive loads. Post-layout results for a 1.8 V-0.18 mum CMOS design show a linear-in-dB programmable gain from 0 to 12 dB with a -3 dB bandwidth above 1.4 GHz and power consumption below 17 mW over all the gain range.     

A multi-purpose CMOS sensor interface for low-power applications

A dedicated low-power CMOS transponder microchip is presented as part of a novel telemetry implant for biomedical applications. This mixed analog-digital circuit contains an identification code and collects information on physiological parameters, i.e., body temperature and physical activity, and on the status of the battery. To minimize the amount of data to be transmitted, a dedicated signal processing algorithm is embedded within its circuitry. All telemetry functions (encoding, modulation, generation of the carrier) are implemented on the integrated circuit. Emphasis is on a high degree of flexibility towards sensor inputs and internal data management, extreme miniaturization, and low-power consumption to allow a long implantation lifetime     

A CCD programmable signal processor

A generic large-coupled device (CCD) signal processor that performs 2.8-billion computations per second with a 10-MHz clock rate is described. The device's concept, design, operation, performance, and applications are reviewed. A dynamic range greater than 42 dB has been demonstrated by the device. This processor can be used as a one-dimensional correlator, a two-dimensional matched filter or a two-layer neural net device. The device demonstrates the flexibility and computational power that is possible using CCD technology     

Mixed-grained CMOS field programmable analog array for smart sensory applications

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays （FPAAs）, which are the analogue counterparts of Field Programmable Gate Arrays （FPGAs）. In this paper, we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory micro- system. The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks （CABs） which house a variety of processing elements especially the proposed fine-grained Core Con- figurable Amplifiers （CCAs）. The high flexible CABs allow the FPAA operating in both continu- ous-time and discrete-time approaches suitable to support variety of sensors. To reduce the nonideal parasitic effects and save area, the fat-tree interconnection network is adopted in this FPAA. The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter. The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth. The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency. And the simulation results also show that the FPAA has good tolerance with wide PVT variations.     

A CMOS mainframe processor with 0.5-μm channel length

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 μm. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0-μm technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability     

A high-speed programmable CMOS interface system combining D/Aconversion and FIR filtering

This paper describes the design, integrated circuit realization, and experimental characterization of a high-speed programmable interface system combining the functions of digital-to-analog (D/A) conversion and FIR filtering. The system comprises four high-speed digital delay lines, with programmable delay length, together with four high-speed steering-current D/A converters with independent digitally-programmable gains. A demonstration prototype chip has been fabricated in a 1.2-μm digital CMOS technology. At 54 MHz conversion rate and digital delay lines clocked at 18 MHz, it consumes 115 mW for a full-scale output current of 13.3 mA at 5 V supply     

A single-chip NMOS dual channel filter for PCM telephony applications

The implementation of a completely monolithic channel filter containing all frequency selective functions associated with a PCM line interface is described. The circuit utilizes switched capacitor techniques. Design of the overall architecture, the individual filter sections, and the operational amplifiers in NMOS technology is described. Experimental results are presented.     

A new green energy interface for telecommunications

Providing electricity to telecom tower can be realised by hybrid green energy systems than extending a power line from grid. For a hybrid energy system, it is important to develop a converter to integrate different power sources and storage elements. Conventional systems use an individual converter for individual source thus leading to a relatively complex configuration, larger component count and reduced system efficiency. To address these issues green energy interface (GEI) converter is used. In this paper, a detailed component wise analysis and performance comparison between conventional and GEI converter using Matlab/Simulink is presented. GEI converter has linear and non-linear components. So, small signal model based on state space averaged model of the GEI topology is obtained. A lab level prototype for the GEI converter with programmable interface controller is implemented and tested under various input conditions to study the performance of the converter during seasonal changes. The simulation and experimental results showed that effective operation and control strategy of the hybrid power supply system.

Abbreviations: BTS: base transceiver station; MSC: mobile switching centre; BSC: base station controller; CAPEX: capital expenditure; OPEX: operational expenditure; GEI: green energy interface     

小型可编程数字信号处理机

本文介绍的一种实时处理的可编程数字信号处理机是采用正交双通道处理,用一组高阶复数FIR滤波器和高阶实数FIR滤波器实现滤波,信噪比和地杂波抑制得到改善,并具有三种恒虚警处理手段。全机由微程序控制。     

A programmable analog CMOS synapse for neural networks

This paper presents a programmable analog synapse for use in both feedforward and feedback neural networks. The synapse consists of two complementary floating-gate MOSFETs which are programmable in both directions by Fowler-Nordheim tunneling. The P-transistor and the N-transistor are programmable independently with pulses of different amplitude and duration, and hence finer weight adjustment is made possible. An experimental 4×4 synapse array has been designed, which in addition has 32 analog CMOS switches and x–y decoders to select a synapse cell for programming. It has been fabricated using a standard 2-m, double-polysilicon CMOS technology. Simulation results confirm that output current of synapse is proportional to the product of the input voltage and weight and also shows both inhibitory and excitatory current. Current summing effect has been observed at the input of a neuron. This array is designed using modular and regular structured elements, and hence is easily expandable to larger networks.     

A programmable focal-plane MIMD image processor chip

An 80×78 pixels vision chip for focal-plane image processing is presented. The chip employs a Multiple-Instruction-Multiple-Data (MIMD) architecture to provide five spatially processed images in parallel. The size, configuration, and coefficients of the spatial kernels are programmable. The chip's architecture allows the photoreceptor cells to be small and parked densely by performing all computations on the read-out, away from the array. The processing core uses digitally programmed current-mode analog computation. Operating at 9.6 K frames/s in 800-lux ambient light, the chip consumes 4 mW from a 2.5-V power supply. Performing 11×11 spatial convolutions, an equivalent computation (5.5 bit scale-accumulate) rate of 12.4 GOPS/mW is achieved using 22 mm² in a 1.2-μm CMOS process. The application of the chip to line-segment orientation detection is also presented     

A low-noise BiCMOS amplifier channel for telecommunications

A low-noise low-pass amplifier channel designed for telecommunications is described. The channel has an 80-kHz corner frequency and total dynamic range of 94 dB. To achieve the high dynamic range, the amplifier channel is constructed with a BiCMOS process and a relative high supply voltage of ±8V is used. To further increase the dynamic range, the baseband amplifier has two branches, a low gain (A = 29 dB) and a high gain (A = 73 dB) branch, comprising a common continuous-time preamplifier and separate antialias filters, switchedcapacitor filters, and postamplifiers. Differential signal processing is used to reduce the effect of common-mode disturbances.     

A software programmable CMOS telephone circuit

A mixed analog-digital IC combining the speech and signaling functions of an analog telephone is described. The realization in a standard 2-μm CMOS process offers the possibility of integrating complex digital functions, such as dual-tone multifrequency (DTMF) generation, in combination with many digital programmable analog circuits . Novel features, such as digital programmable level control, DC characteristics, frequency response, input impedance, and sidetone path, are implemented. These attributes offer a flexible solution for the different international requirements, with only a few external components. Software control of analog and digital functions and the high degree of integration enable telephone manufacturers to produce a quality feature phone with a minimum of components, and therefore with high reliability and low cost     

A 0.8-μm CMOS two-dimensional programmable mixed-signalfocal-plane array processor with on-chip binary imaging and instructionsstorage

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. On-chip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-μm single-poly double-metal technology and features 2-μs operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations     

一种双模式的CMOS现场可编程模拟阵列的分析与设计

本篇文章提出了基于采用高度灵活的互连盒的互连网络的一种新型的现场可编程模拟阵列(FPAA)结构,该结构可以在双模式下工作包括离散时间模式和连续时间模式,以追求在不同应用场合下的性能要求。高度灵活的互连盒中的开关不仅用来作为可编程开关还直接作为开关电容中电荷转移的开关来使用,大大减少了离散时间模式下信号路径上的开关,提高了整体电路的性能。该款FPAA采用0.18um CMOS工艺,3.3V电源电压。后仿结果显示互连网络的最大带宽可达265MHz, 从示例的测试结果可以看出该款FPAA在连续时间模式下可工作在2MHz信号带宽下,无杂散动态范围可达54dB, 离散时间工作模式下的处理精度可达96.4%。