一种新型的信道纠错编码——之型码

提出了一种新型的纠错码－之型码,它可形成非常简捷的罗软输入／软输出译码规则,而且仿真结果表明,其性能在误比特率为10^-5处距香农理论极限仅0．9dB。     

一种基于之型分量码的系统GLDPC码

本文以规则低密度生成矩阵码为基础,构建了一种以之型码为分量码的系统广义低密度奇偶校验(Generalized Low-Density Parity-Check,GLDPC)码,称为ZS-GLDPC码.该码具有线性编码复杂度,可采用和积译码算法实现迭代译码,其译码复杂度低于以汉明码为分量码的GLDPC码.在均匀交织器的前...     

RS码与LDPC码的联合迭代译码

针对RS码与LDPC码的串行级联结构,提出了一种基于自适应置信传播(ABP)的联合迭代译码方法.译码时,LDPC码置信传播译码器输出的软信息作为RS码ABP译码器的输入;经过一定迭代译码后,RS码译码器输出的软信息又作为LDPC译码器的输入.软输入软输出的RS译码器与LDPC译码器之间经过多次信息传递,译码性能有很大提高.码长中等的LDPC码采用这种级联方案,可以有效克服短环的影响,消除错误平层.仿真结果显示:AWGN信道下这种基于ABP的RS码与LDPC码的联合迭代译码方案可以获得约0.8 dB的增益.     

LDPC码全并行译码器的设计与实现

本论文用可编程逻辑器件(FPGA)实现了一种低密度奇偶校验码(LDPC)的编译码算法.采用基于Q矩阵LDPC码构造方法,设计了具有线性复杂度的编码器. 基于软判决译码规则,采用全并行译码结构实现了码率为1/2、码长为40比特的准规则LDPC码译码器,并且通过了仿真测试.该译码器复杂度与码长成线性关系,与Turbo码相比更易于硬件实现,并能达到更高的传输速率.     

乘积码基于相关运算的迭代译码

乘积码是一种能以Turbo码的思想实现译码的级联码，具有一般编码无法达到的纠错能力。本文提出一种新的乘积码迭代译码算法，其核心思想是通过输出软信息与接收软信息进行线性迭加的方式来实现反馈，此时只须提供-1和1组成的软输出矩阵就能获得很高的编码增益，仿真表明，将子译码器译码后的结果再进行一次相关运算作为软输出，译码性能可以得到进一步的提高。     

中长帧非规则LDPC码译码器的FPGA实现

LDPC(低密度奇偶校验码)是一种优秀的线性分组码,是目前距香农限最近的一类纠错编码。与Turbo码相比,LDPC码能得到更高的译码速度和更好的误码率性能,从而被认为是下一代通信系统和磁盘存储系统中备选的纠错编码。简要介绍了适于硬件实现的LDPC码译码算法,并基于软判决译码规则,使用Verilog硬件描述语言,在X ilinx V irtex2 6000 FPGA上实现了码率为1/2、帧长504bit的非规则LDPC码译码器。     

一种乘积码译码器设计方案的研究

介绍了一种乘积码迭代译码器的硬件设计方案。基于软判决译码规则,使用VHDL硬件描述语言,提出了基于Modelsim6.Oa仿真平台的两维乘积码的EDA实现方法,给出了仿真波形,迭代次数为四次时最大译码速率可达到50Mbit/s,并通过了在Xilinx公司的FPGA芯片XC2S200上的综合验证实验。该译码器的功能仿真和硬件实现都证明了这种方案的可行性和正确性。     

一种确定Turbo乘积码迭代因子的方法

提出一种确定Turbo乘积码迭代因子的算法。建立信道模型,生成测试软信息R;生成一组备选迭代因子向量,在备选迭代因子空间里用MATLAB仿真Chase-Pyndiah迭代译码算法流程,选择最优的迭代因子;迭代因子优劣的判据为迭代译码器的误码率以及迭代次数。实验结果表明,最优迭代因子有效地加速了迭代译码器的收敛速度,降低了译码的功耗。     

不同译码器结构对Turbo码性能的影响

文章给出了两种译码顺序不同的Ｔｕｒｂｏ码译码器,并通过软判决维特比算法作译码业比较两种结构的译码效果。     

LDPC码译码器的设计与实现

由于传统的LLR BP译码算法不易于FPGA实现,为了降低实现复杂度,采用一种改进的LLR BP译码实现方法,设计了一种码长为40、码率为0.5的规则LDPC码译码器,并完成了FPGA仿真实现.仿真和综合的结果表明,所设计的译码器吞吐量达到15.68 Mbit/s,且译码器的资源消耗适中.     

Zigzag codes and concatenated zigzag codes

This paper introduces a family of error-correcting codes called zigzag codes. A zigzag code is described by a highly structured zigzag graph. Due to the structural properties of the graph, very low-complexity soft-in/soft-out decoding rules can be implemented. We present a decoding rule, based on the Max-Log-APP (MLA) formulation, which requires a total of only 20 addition-equivalent operations per information bit, per iteration. Simulation of a rate-1/2 concatenated zigzag code with four constituent encoders with interleaver length 65 536, yields a bit error rate (BER) of 10^-5 at 0.9 dB and 1.3 dB away from the Shannon limit by optimal (APP) and low-cost suboptimal (MLA) decoders, respectively. A union bound analysis of the bit error probability of the zigzag code is presented. It is shown that the union bounds for these codes can be generated very efficiently. It is also illustrated that, for a fixed interleaver size, the concatenated code has increased code potential as the number of constituent encoders increases. Finally, the analysis shows that zigzag codes with four or more constituent encoders have lower error floors than comparable turbo codes with two constituent encoders     

利用域间映射的多元QC-LDPC码构造

通过定义有限域间的映射关系,提出了一种低复杂度的多元准循环奇偶校验码( QC-LDPC )的构造方法。利用这种方法可将较高阶数有限域的校验矩阵映射到指定的较低有限域上,且能保持原矩阵的结构性与稀疏特性。所构造的多元LDPC码不仅具有较低的译码复杂度且具有准循环特性,在硬件上也易于用移位寄存器实现。在高斯白噪声( AWGN)信道下的仿真结果表明,所构造的多元QC-LDPC码具有良好的编译码性能。当误码率为10-6时,码率为0.765的QC-LDPC码在目标域GF(8)上能获得0.2 dB的性能增益。     

一种基于增强奇偶校验码级联极化码的新型编译码方法

极化码作为一种纠错码,具有较好的编译码性能,已成为5G短码控制信道的标准编码方案。但在码长较短时,其性能不够优异。提出一种基于增强奇偶校验码级联极化码的新型编译码方法,在原有的奇偶校验位后设立增强校验位,对校验方程中信道可靠度较低的信息位进行双重校验,辅助奇偶校验码在译码过程中对路径进行修剪,以此提高路径选择的可靠性。仿真结果表明,在相同信道、相同码率码长下,本文提出的新型编译码方法比循环冗余校验(cyclic redundancy check,CRC)码级联极化码、奇偶校验(parity check,PC)码级联极化码误码性能更优异。在高斯信道下,当码长为128、码率为1/2、误码率为10-3时,本文提出的基于增强PC码级联的极化码比PC码级联的极化码获得了约0.3dB增益,与CRC辅助的极化码相比获得了约0.4 dB增益。     

Asymptotic performance of single parity-check product codes

This article investigates the asymptotic performance of single parity-check (SPC) product codes (PCs) from a decoding point of view. Specifically, the probability of bit error is bounded before and after the decoding of each dimension, similar to the analysis of "iterated codes" by Elias (1954). It is shown that the asymptotic probability of bit error can be driven to zero as the number of dimensions, and hence the block length, increases at signal-to-noise ratios (SNRs) within 2 dB of capacity over the additive white Gaussian noise (AWGN) channel.     

Novel construction of quasi-cyclic low-density parity-check codes with variable code rates for cloud data storage systems

This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10⁻¹⁰ at 3.5 dB E_b/N₀ than conventional LDPC codes, which showed a BER of 10⁻⁷ at 3 dB E_b/N₀. Subsequently, implementation of the proposed QC-LDPC code in a software-defined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10⁻⁶ at 4.2 dB E_b/N₀ was achieved. Then, the performance of the proposed codes based on their encoding–decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed–Solomon codes.     

系统极化码的置信传播译码性能分析

置信传播( BP)算法可以为系统极化码提供软信息作为判决依据,也可以为系统极化码在级联迭代译码中提供交换软信息。在详细描述基于信道极化结构的置信传播算法基础上,比较了系统极化码在软信息判决方法和极化编码判决方法下错误率性能的差异。仿真结果表明,软信息判决方法可以提高系统极化码的误比特率,在高信噪比下误帧率方面也略有提高。     

Bidirectional breadth-first algorithms for the decoding ofconvolutional codes

Bidirectional multiple-path tree searching algorithms for the decoding of convolutional codes are presented. These suboptimal coding algorithms use a multiple-path breadth-first bidirectional tree exploration procedure and long-memory convolution codes. It is shown that, compared to the usual M-algorithm, the bidirectional exploration considerably reduces the bit error propagation due to correct path loss. Computer simulations using rate-1/2 codes over binary symmetric channels are used to analyze the effect of the number of path extensions, code memory, and frame length on the bit error probability. The results show that with a bit error probability of 10^-5, coding gains on the order of 2 dB over the M-algorithm and 1 dB over a Viterbi decoder of equivalent complexity can be achieved     

Iterative decoding of parallel and serial concatenated single parity check product codes

An efficient, iterative soft-in-soft-out decoding scheme is employed for the parallel and serially concatenated single parity check (SPC) product codes, which has very low complexity, requiring only two addition-equivalent-operations per information bit. For a rate 0.8637 of parallel concatenated SPC product code, a performance of BER=10/sup -5/ at E/sub b//N/sub 0/=3.66 dB can be achieved using this decoding scheme, which is within 1 dB from the Shannon limit.     

一种动态加权的LDPC译码方法

为了加快低密度奇偶校验（LDPC）码的译码速度,有效改善LDPC码的译码性能,针对校验节点更新过程中的对数似然比（LLR）值的大小,设计了一种LDPC码的动态加权译码方法。以IEEE 802.16e标准的奇偶校验矩阵为例,根据LLR值的变化规律,利用增长因子和抑制因子对和积译码算法和最小和译码算法进行动态加权。仿真结果显示,基于动态加权的译码方法相对于传统译码方法误码率都有明显改进,译码复杂度也有所降低。