Template fabrication for the 32 nm node and beyond

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and flash imprint lithography (S-FIL^™) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates.This paper addresses steps required to achieve resolution at or below 32 nm. Gaussian-beam writers are now installed in mask shops and are being used to fabricate S-FIL templates. Although the throughput of these systems is low, they can nevertheless be applied towards applications such as unit process development and device prototyping.Resolution improvements were achieved by optimizing the ZEP520A resolution and exposure latitude. Key to the fabrication process was the introduction of thinner resist films and data biasing of the critical features. By employing a resist thickness of 70 nm and by negatively biasing features as much as 18 nm, 28 nm half-pitch imprints were obtained. Further processing improvements show promise for achieving 20 nm half-pitch features on a template.     

Multi-gate devices for the 32 nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased V_T statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on, planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET-based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.     

Experimental study of multilayer SiCN barrier film in 45/40 nm technological node and beyond

With feature size of device scaled down 45 nm technological node and beyond, the backend of the line (BEOL) faces too many problems such as resistance–capacitance (RC) delay, crosstalk noise, and power consumption. In order to improve RC delay, the SiCN dielectric constant had to further decrease through introducing C₂H₄ gas to increase its carbon content. The SiCN_kI (k ~ 5.3) and SiCN_kII (k ~ 3.8) were characterized by spectroscopic ellipsometer, fourier transform infrared spectroscopy (FTIR), Rutherford backscattering spectrometry–hydrogen forward scattering (RBS–HFS), X-ray reflectivity (XRR), Hg probe, four point bending (4-PB) test, scanning electron microscope (SEM), and transmission electron microscope (TEM). Results indicated that the hardness and modulus and density of the SiCN_kII were lower than that of the SiCN_kI. RBS–HFS and FTIR examination indicated that SiCN_kII barrier film had high carbon content and terminating CH₃ group to cause low cross-linking and density of dielectric films resulting in large volume. 4-PB test combined with transmission electron microscope (TEM) examination demonstrated that the crack occurred in the interface between SiCN_kII film/SiCN_kI bilayer barrier film and low k film. After adding SiCNkI barrier film, no crack was found using SiCN_kI/SiCN_kII film/SiCN_kI tri-layer barrier film. In addition, the capacitance and RC reduction ratios were improved to about 7–8% using the SiCN_kII/SiCN_kI bilayer barrier film.     

The influence of 1 nm AlN interlayer on properties of the Al0.3Ga0.7N/AlN/GaN HEMT structure

The sheet carrier concentrations, conduction band profiles and amount of free carriers in the barriers have been determined by solving coupled Schrödinger and Poisson equation self-consistently for coherently grown Al_0.3Ga_0.7N/GaN and Al_0.3Ga_0.7N/AlN/GaN structures on thick GaN. The Al_0.3Ga_0.7N/GaN heterojunction structures with and without 1 nm AlN interlayer have been grown by MOCVD on sapphire substrate, the physical properties for these two structures have been investigated by various instruments such as Hall measurement and X-ray diffraction. By comparison of the theoretical and experimental results, we demonstrate that the sheet carrier concentration and the electrons mobility would be improved by the introduction of an AlN interlayer for Al_0.3Ga_0.7N/GaN structure. Mechanisms for the increasing of the sheet carrier concentration and the electrons mobility will be discussed in this paper.     

Impact of process parameters on circuit performance for the 32 nm technology node

As IC dimensions scale down to the 32 nm technology node, interconnect is more than ever the most limiting factor affecting overall circuit performance. The influence of all involved process parameters were studied as a function of target application through electromagnetic and time domain simulations, and compared to the impact of driver characteristics. As a result, an optimization of the BEOL stack was performed to propose process and material recommendations meeting electrical specifications for most circuit applications.     

神经MOS晶体管在A/D和D/A转换器中的应用

神经MOS晶体管是一种具有多输入栅加权信号控制和阈值可调控的高功能度的新型器件。以神经MOS晶体管的Pspice宏模型为模拟和验证的工具,讨论了基于这种器件的A/D和D/A转换器的设计思想和方法,证明了他能很大程度地减少晶体管数目,简化电路,对实现高密度集成的ULSI系统的设计和实现有重要意义。     

D/A和A/D转换器型谱的品种优化分析

本文从D/A与A/D转换器的基本概念和制造技术着手概述,特别对D/A和A/D转换器的应用之主要选择因素,进行了着重说明。随后,提出了D/A和A/D转换器优化品种的原则意见。     

考虑源漏隧穿的DG MOSFET弹道输运及其模拟

在经典弹道输运模型中引入源漏隧穿 (S/ D tunneling) ,采用 WKB方法计算载流子源漏隧穿几率 ,对薄硅层(硅层厚度为 1nm) DG(dual gate) MOSFETs的器件特性进行了模拟 .模拟结果表明当沟道长度为 10 nm时 ,源漏隧穿电流在关态电流中占 2 5 % ,在开态电流中占 5 % .随着沟道长度进一步减小 ,源漏隧穿比例进一步增大 .因此 ,模拟必须包括源漏隧穿 .     

FinFET based SRAM bitcell design for 32 nm node and below

The methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves consideration of both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V_ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1 μm² below 32 nm node.     

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Static testing of analog‐to‐digital (A/D) and digital‐to‐analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built‐in self‐test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.     

一种用于人体无线传感器网络节点的8比特低功耗逐次逼近模数转换器

本文描述了一款用于人体无线传感器网络节点中的8比特低功耗模数转换器。该转换器采用了电荷共享型结构。本模数转换器采用0.18um CMOS工艺制造。测试结果表明,当采样速率从64KHz 变化到1.5MHz,模数转换器有效精度稳定在7.4比特,其功耗变化范围为10.8uW到225.7uW     

MAX1148型高精度14位串行A/D转换器

MAX1148是Maxim公司2005年最新推出的14位串行模/数转换器.文中介绍了MAX1148的特点、结构和工作原理,给出了它在8位CPU为核心的数据采集系统中的应用实例.     

A low power 8-bit successive approximation register A/D for a wireless body sensor node

A power efficient 8-bit successive approximation register(SAR)A/D for the vital sign monitoring of a wireless body sensor network(WBSN)is presented.A charge redistribution architecture is employed.The prototype A/D is fabricated in 0.18 μm CMOS.The A/D achieves 7.SENOB with sampling rate varying from 64 kHz to 1.5 MHz.The power consumption varies from 10.8 to 225.7 μW.     

基于STM32的MIT-BIH心电数据的D/A回放

设计基于STM32的MIT-BIH心电数据D/A回放,对整体设计方案、硬件组成、软件设计等进行了介绍。通过读取心电数据将其进行D/A转换,输出波形与原始波形进行比较,较好地实现了回放功能。由此可见,该系统的性能指标达到了设计要求。能很好地实现心电数据回放,为一系列心电算法的仿真实践及实时心电监护仪的研制打好了基础。     

利用A/D和D/A实现频率变换的技术分析

通过建立A/D、D/A的数学模型,推导了A/D、D/A实现变频的基本公式,分析了量化噪声和变频损失,总结了其主要特点及其与模拟混频器的区别,说明A/D和D/A实现频率变换是切实可行的,在进行模数、数模转换的同时实现变频,有利于节省器件,简化电路。     

A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32 nm node

The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such as the CMOS 32 nm in this work. This paper presents a local ESD protection structure based on dynamic triggered SCR and qualifies through TLP and vf-TLP for GO1 = 1 V and GO2 = 1.8 V power domain.     

A/D转换技术的应用与发展

首先分别介绍了当前六大模数转换技术的工作原理、电路结构、性能特点及应用领域,通过从转换速率、转换精度、分辨率、功耗、价格、面积等指标进行分析,将物理结构的设计与实际性能结合比较,总结出各自适合的应用领域.然后,根据对现有模数转换技术特点的分析及实际应用中对模数转换器性能的要求,对当前A/D转换技术向着高性能、低功耗、结构简单方向发展的趋势进行了预测.     

SEM-based nanoprobing on 32 and 28 nm CMOS devices challenges for semiconductor failure analysis

This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28 nm and larger technology nodes.     

基于高速A/D转换器的视频数据采集系统

针对视频采集系统需要对摄像头输出的复合视频信号进行快速转化、采样、存储的要求,设计基于高速A/D转换器TLC5510的视频采集系统。模拟视频信号通过A/D转换器转化为8位灰度值,16位微处理器MC9S12DG128B通过普通IO口,控制FIFO存储器uPD42280写入和读取A/D转换结果,实现视频图像数据的高精度采集。分析了主要芯片的工作原理及时序,描述了软件控制图像数据采集流程。并将采得数据经过处理,与实际图像对比。实验结果表明,该系统在单行扫描时间50μs内能采集160个以上的有效像素点,成像质量高,能满足简单图像处理算法对数据的要求。     

一种用于ADC减少插值误差的预放大器

在分析折叠内插ADC预放大电路非线性误差的基础上,设计了一种适用于折叠内插ADC的新型预放大器,有利于减少插值非线性。采用0.35μmCMOS工艺,在3.3V电源电压下进行仿真。结果表明,在0.85V到2.45V输入范围内,预放大器过零点对应的输出电压保持在2.6V,0.1%的容差范围内,建立时间为4.2ns,有利于提高插值精度。