A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration

Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10-b 120-Msample/s pipelined analog-to-digital converter (ADC). Offset mismatch between channels is overcome with a random chopper-based offset calibration. Gain mismatch and sample-time error are overcome with correlation-based algorithms, which drive the correlation between a signal and its chopped image or its chopped and delayed image to zero. Test results show that, with a 0.99-MHz sinusoidal input, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.8 dB, a peak integral nonlinearity of 0.88 least significant bit (LSB), and a peak differential nonlinearity of 0.44 LSB. For a 39.9-MHz sinusoidal input, the ADC achieves a peak SNDR of 50.2 dB. The active area is 5.2 mm/sup 2/, and the power dissipation is 234 mW from a 3.3-V supply.     

A 10-b 40-Msample/s BiCMOS A/D converter

A fully-differential, 10-b, 40-Msample/s pipelined analog-to-digital converter (ADC) has been developed and tested. The converter exhibits a signal-to-(noise+distortion) ratio (SNDR) of 57.1 dB and consumes <400 mW of power from a single 5 V supply. The converter can digitize not only a fully-differential but also a single-ended input signal over a wide input range with little variation in converter performance. In addition, a full-power bandwidth (FPBW) of >250 MHz is made possible with the open-loop sampling scheme     

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm²     

A pipelined 5-Msample/s 9-bit analog-to-digital converter

A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.     

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.     

A 13-b 10-Msample/s ADC digitally calibrated with oversamplingdelta-sigma converter

Two key techniques necessary to digitally calibrate multistep or pipelined converters are demonstrated in a differential 5-V, 13-b, 10-Msample/s analog-to-digital converter (ADC). One technique, called code-error calibration, is to linearize the transfer characteristic of digital-to-analog converters (DAC's) while the other, called gain-error proration, is to evenly distribute interstage gain errors over the full conversion range. The core of the former technique is an oversampling delta-sigma ratio calibrator working synchronously with the converter. This digital calibration process constantly tracks and updates the code errors without interfering with the normal operation. The prototype converter fabricated using a 1.4-μm BiCMOS process consumes 360 mW with a 5-V single supply and exhibits a signal-to-noise ratio of 71 dB and a maximum end-point integral nonlinearity of 1.8 LSB at a 13-b level. The proposed techniques can be incorporated into general multistep or pipelined ADC's without sacrificing the conversion speed     

A monolithic CMOS 20-b analog-to-digital converter

The authors present a monolithic 20-b analog-to-digital converter (ADC) based on an oversampling feedback architecture. The converter consists of a time-continuous integrator at the input, a pulsewidth modulator in the forward branch of the loop (corresponding to a 10-b ADC), and a 1-b DAC (digital-to-analog converter) to generate the feedback voltage. The digital evaluation is carried out with a uniformly weighted rectangular window filter. The circuit is implemented in a standard 2-μm CMOS n-well process and requires 14 mm² of silicon, including the pads. Measurement results are presented that demonstrate the feasibility of this architecture for 20-b accuracy. The complete circuit has a power consumption of 6.7 mW     

A 12-b 5-Msample/s two-step CMOS A/D converter

Two-step flash architectures are an effective means of realizing high-speed high-resolution analog-to-digital converters (ADCs) because they can be implemented without the need for operational amplifiers having either high gain or a large output swing. Moreover, with conversion rates approaching half those of fully parallel designs, such half-flash architectures provide both a relatively small input capacitance and low power dissipation. The authors describe the design of a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1-μm CMOS technology. Configured as a fully differential circuit, the converter performs a 7-b coarse flash conversion followed by a 6-b fine flash conversion. Both analog and digital error correction are used to achieve a resolution of 12 b. The converter dissipates only 200 mW from a single 5-V supply and occupies an area of 2.5 mm × 3.7 mm     

An 8-bit 80-Msample/s pipelined analog-to-digital converter withbackground calibration

An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm ² in a single-poly 0.5 μm CMOS technology     

A 10-b 100-Msample/s pipelined subranging BiCMOS ADC

A 10-b 100-Msample/s pipelined subranging analog-digital converter (ADC) has been achieved. Such technologies as a pipelined subranging scheme, a track-and-hold amplifier (THA) with current-switching sampling gates, a 94-dB dc open-loop gain, a 335-MHz unity-gain frequency op amp, and a carry-look-ahead adder for digital error correction are presented. The 3.4-mm×5.6-mm ADC chip was fabricated using a 0.8-μm BiCMOS process and operates with 950-mW power dissipation from a single -5-V power supply     

Fully bipolar, 120-Msample/s 10-b track-and-hold circuit

Describes the design and experimental results of a fully bipolar track-and-hold (T&H) circuit for use in video applications. A fully differential, open-loop approach has been chosen in order to meet the specifications with respect to track-to-hold step, droop rate, and hold-mode feedthrough. In order to obtain maximum high-frequency performance, p-n-p transistors have been omitted from the design. The T&H circuit has been realized in a 3-GHz f/sub T/ bipolar production process with a minimum emitter size of 2*9 mu m/sup 2/. The die size is 0.25 mm/sup 2/, consuming 40 mW from a single 5-V power supply. Ten-bit performance has been measured up to 12-Msample/s full-Nyquist sampling rate. At 200 Msample/2, 8-b performance has been observed over the full-Nyquist band.<>     

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-/spl mu/m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8/spl times/3.6 mm/sup 2/, and the power consumption is 370 mW with a single 2.5-V supply.     

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.     

A 10-b, 100-MS/s CMOS A/D converter

A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-μm CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same     

A 15-b, 5-Msample/s low-spurious CMOS ADC

A 5-5-5-6-b pipelined analog-to-digital converter (ADC) architecture alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-b most significant bit (MSB) stages are digitally calibrated to implement a 15-b, 5-Msample/s low-spurious ADC using 1.4-μm CMOS. A skip-and-fill algorithm with nonlinear interpolation also opens up the possibility of calibrating ADC's in the background synchronously with their normal operation. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.75/-0.6 least significant bit (LSB), an integral nonlinearity (INL) of +1.77/-1.58 LSB, and all spurious components are suppressed to below -93 dB when sampled at 5 MHz. The chip occupies 27 mm², and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing     

A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within ±0.25 LSB at 15 b, and the INL was measured to be within ±1.25 LSB at 15 b. The die area is 9.3 mm×8.3 mm and operates on ±4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4-μm BiCMOS process     

A low-power 12-b analog-to-digital converter with on-chip precisiontrimming

The design and performance of a 12-b charge redistribution analog-to-digital converter (ADC) is described. The architecture is chosen to minimize power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a 1-μm CMOS process. It converts at a 200-kHz rate with a power dissipation of 10 mW     

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.     

A 400-Msample/s, 6-b CMOS folding and interpolating ADC

A 400-Msample/s, 6-bit CMOS folding and interpolating analog-to-digital converter (ADC) is described. A low-impedance current-mode approach is adopted. Current-division interpolation incorporated within the folders allows fast operation and is compatible with low supply voltages. This interpolation scheme, together with a short aperture comparator, gives good performance for input frequencies up to one-quarter of the sampling rate without using a sample and hold. For simplicity, the ADC uses only a single clock and its complement. The device is implemented in a 0.5 μm BiCMOS technology using only CMOS devices. The converter occupies 0.6 mm² and dissipates 200 mW from a 3.2 V supply     

A 20-Msample/s switched-capacitor finite-impulse-response filterusing a transposed structure

A programmable four-tap analog finite-impulse-response filter for use in a decision-feedback equalizer has been realized in a 2-μm double-poly CMOS process. It uses a modified transposed structure and double sampling to minimize power dissipation. Also, it uses programmable-gain sample-and-hold amplifiers with a constant feedback factor, input capacitance, and load to reduce the performance variation as a function of programming. The filter is fully differential, occupies an active area of 11.8 mm², and dissipates 56.5 mW