Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.     

Effect of Fluoride‐based Plasma Treatment on the Performance of AlGaN/GaN MISHFET

This paper demonstrates the effect of fluoride‐based plasma treatment on the performance of Al₂O₃/AlGaN/GaN metal‐insulator‐semiconductor heterostructure field effect transistors (MISHFETs) with a T‐shaped gate length of 0.20 μm. For the fabrication of the MISHFET, an Al₂O₃ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using CF₄ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the Al₂O₃ gate dielectric layer to the plasma environment. The thickness of the Al₂O₃ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off‐state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.     

0.25-μm pseudomorphic HEMTs processed with damage-free dry-etchgate-recess technology

Damage-free, dry-etched 0.25-μm T-shape gate pseudomorphic InGaAs channel HEMTs have been demonstrated. A Freon-12-based discharge was used in either electron cyclotron resonance (ECR) or reactive ion etching (RIE) systems to perform the gate recess process. Etching selectivity of more than 200 was obtained between the GaAs cap layer and the underlying AlGaAs donor layer. Self-bias voltages of -30 to -50 V were used in the etching process to minimize the damage. Pre- and post-etch clean steps were utilized to achieve uniform etch and removal of any dry-etch-related residues. Schottky diodes fabricated on n-GaAs subjected to either dry or wet etching showed no differences of barrier height, zero-bias depletion depth, and ideality factor. By using the dry etch for gate recess, very tight threshold voltage uniformity was obtained. The devices showed I-V characteristics comparable to that of devices fabricated with a wet chemical process     

A new two-dimensional C-V model for prediction of maximum frequency of oscillation (fmax) of deep submicron AlGaN/GaN HEMT for microwave and millimeter wave applications

An analytical two-dimensional capacitance-voltage model for AlGaN/GaN high electron mobility transistor (HEMTs) is developed, which is valid from a linear to saturation region. The gate source and gate drain capacitances are calculated for 120 nm gate length including the effects of fringing field capacitances. We obtain a cut-off frequency (f_T) of 120 GHz and maximum frequency of oscillations (f_max) of 160 GHz. The model is very useful for microwave circuit design and analysis. Additionally, these devices allow a high operating voltage V_DS, which is demonstrated in the present analysis. These results show an excellent agreement when compared with the experimental data.     

Electrical Characteristics of Triple‐Gate RSO Power MOSFET (TGRMOS) with Various Gate Configurations and Bias Conditions

In this paper, we propose a triple‐gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage (BV_DS) and on‐state current (I_D,MAX), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer (SiO₂) of a conventional RSO power MOSFET is changed to a multilayered insulator (SiO₂/SiN_x/TEOS). The inserted SiN_x layer can create the selective etching of the TEOS layer between the gate oxide and poly‐Si layers. After additional oxidation and the poly‐Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as BV_DS and I_D,MAX, simulation studies are performed on the function of the gate configurations and their bias conditions. BV_DS and I_D,MAX are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15‐V gate voltage. This I_D,MAX variation indicates the specific on‐resistance modulation.     

Fabrication and Performance of 0.25-$mu$m Gate Length Depletion-Mode GaAs-Channel MOSFETs With Self-Aligned InAlP Native Oxide Gate Dielectric

The fabrication and performance of 0.25- mum gate length GaAs-channel MOSFETs using the wet thermal native oxide of InAlP as the gate dielectric are reported. A fabrication process that self-aligns the gate oxidation to the gate recess and metallization to reduce the source access resistance is demonstrated for the first time. The fabricated devices exhibit a peak extrinsic transconductance of 144 mS/mm, an on-resistance of 3.46 Omega-mm, and a threshold voltage of -1.8 V for typical 0.25 -mum gate devices. A record cutoff frequency of 31 GHz for a GaAs-channel MOSFET and a maximum frequency of oscillation f_max of 47 GHz have also been measured.     

最大振荡频率为200GHz的蓝宝石衬底AlGaN/GaN HEMT

报道了最大振荡频率为200 GHz的基于蓝宝石衬底的AlGaN/GaN高电子迁移率晶体管(HEMT).外延材料结构采用InGaN背势垒层来减小短沟道效应,器件采用凹栅槽和T型栅结合的工艺,实现了Ka波段AlGaN/GaNHEMT.器件饱和电流达到1.1 A/mm,跨导为421 mS/mm,截止频率(fT)为30 GHz...     

20.7% efficient ion‐implanted large area n‐type front junction silicon solar cells with rear point contacts formed by laser opening and physical vapor deposition

In this work, we report on ion‐implanted, high‐efficiency n‐type silicon solar cells fabricated on large area pseudosquare Czochralski wafers. The sputtering of aluminum (Al) via physical vapor deposition (PVD) in combination with a laser‐patterned dielectric stack was used on the rear side to produce front junction cells with an implanted boron emitter and a phosphorus back surface field. Front and back surface passivation was achieved by thin thermally grown oxide during the implant anneal. Both front and back oxides were capped with SiN_x, followed by screen‐printed metal grid formation on the front side. An ultraviolet laser was used to selectively ablate the SiO₂/SiN_x passivation stack on the back to form the pattern for metal–Si contact. The laser pulse energy had to be optimized to fully open the SiO₂/SiN_x passivation layers, without inducing appreciable damage or defects on the surface of the n⁺ back surface field layer. It was also found that a low temperature annealing for less than 3 min after PVD Al provided an excellent charge collecting contact on the back. In order to obtain high fill factor of ~80%, an in situ plasma etching in an inert ambient prior to PVD was found to be essential for etching the native oxide formed in the rear vias during the front contact firing. Finally, through optimization of the size and pitch of the rear point contacts, an efficiency of 20.7% was achieved for the large area n‐type passivated emitter, rear totally diffused cell. Copyright © 2014 John Wiley & Sons, Ltd.     

最大振荡频率为200 GHz的蓝宝石衬底AlGaN/GaN HEMT

本文报道了fmax为200GHz的基于蓝宝石衬底的AlGaN/GaN 高电子迁移率晶体管（HEMT）。外延材料结构采用了InGaN背势垒层来减小短沟道效应,器件采用了凹栅槽和T型栅结合的工艺,实现了Ka波段AlGaN/GaN HEMT。器件饱和电流达到1.1A/mm,跨导为421mS/mm,截止频率（fT）为30GHz,最大振荡频率（fmax）为105GHz。采用了湿法腐蚀工艺将器件的Si3N4钝化层去除后,器件的Cgs和Cgd减小,器件截止频率提高到50GHz,最大振荡频率提高到200GHz。     

Laser induced defects in laser doped solar cells

Laser doping offers a promising method to define selective emitters for solar cells. Its main advantage is the localised nature of the laser beam, which allows melting of the surface area without heating the bulk. The ability to perform this process over a dielectric film offers further benefits, such as the possibility of creating self‐aligned metallisation patterns simultaneously with the selective emitter formation. However, laser induced defects, contaminations and discontinuities in the selective emitter can reduce solar cell performance. In this work the influence of different dielectric films on defect formation is investigated. It was found that a thin oxide beneath the SiN_x improves the implied open circuit voltage of the solar cells for a wide range of laser output powers. Fewer defects were observed when using this SiO₂/SiN_x stack compared to the standard single SiN_x anti‐reflection coating layer. It was also found that the recrystallised silicon layer grows epitaxially according the substrate orientation. No dislocation or stacking faults were observed in deeper areas using transmission electron microscopy, although some defects were observed near the surface. Electron beam induced current images revealed discontinuities in junctions formed with high laser powers. We conclude that micro‐cracks create these discontinuities, which can potentially induce shunts. Finally, laser doped solar cells with a standard SiN_x and with a double SiO₂/SiN_x stack layer as anti‐reflection coating were compared. An efficiency of 18.4% on a large area commercial grade p‐type CZ substrate was achieved. Copyright © 2010 John Wiley & Sons, Ltd.     

Low-frequency noise properties of selectively dry etched InP HEMT's

The low-frequency noise of lattice-matched InAlAs/InGaAs/InP high electron mobility transistors (HEMT's) gate recess etched with a highly selective dry etching process and with conventional wet etching were studied at different gate and drain biases for the temperature range of 77-340 K. The measurements showed a significantly lower normalized drain current 1/f noise for the dry etched HEMT's under all bias conditions. No difference in the normalized gate current 1/f noise could be observed for the two device types. By varying the temperature, four electron traps could be identified in the drain current noise spectra for both dry and wet etched devices. No additional traps were introduced by the dry etching step. The concentration of the main trap in the Schottky layer is one order of magnitude lower for the dry etched HEMT's. No hydrogen passivation of the shallow donors was observed in these devices. We presume hydrogen passivation of the deep levels as the cause for the trap density reduction. The kink effect in the dry etched HEMT's was observed to be reduced significantly compared with wet etched devices which gives further evidence of trap passivation during dry etching. These results show that dry etched InP HEMT's have suitable characteristics for the fabrication of devices for noise sensitive applications     

以非晶硅为硬掩膜的TaN金属栅的选择性湿法腐蚀

提出了一种在HfSiON介质上,采用非晶硅为硬掩膜的选择性去除TaN的湿法腐蚀工艺。由于SC1(NH4OH:H2O2:H2O)对金属栅具有合适的腐蚀速率且对硬掩膜和高K材料的选择比很高,所以选择它作为TaN的腐蚀溶液。与光刻胶掩膜和TEOS硬掩膜相比,因非晶硅硬掩膜不受SC1溶液的影响且很容易用NH4OH溶液去除（NH4OH溶液对TaN和HfSiON薄膜无损伤）,所以对于在HfSiON介质上实现TaN的选择性去除来说非晶硅硬掩膜是更好的选择。另外,在TaN金属栅湿法腐蚀和硬掩膜去除后, 高K介质的表面是光滑的,这可防止器件性能退化。因此,采用非晶硅为硬掩膜的TaN湿法腐蚀工艺可以应用于双金属栅集成,实现先淀积的TaN金属栅的选择性去除。     

AlGaN/GaN HEMTs with 0.2μm V-gate recesses for X-band application

正AlGaN/GaN HEMTs with 0.2μm V-gate recesses were developed.The 0.2μm recess lengths were shrunk from the 0.6μm designed gate footprint length after isotropic SiN deposition and anisotropic recessed gate dry etching.The AlGaN/GaN HEMTs with 0.2μm V-gate recesses on sapphire substrates exhibited a current gain cutoff frequency f_t of 35 GHz and a maximum frequency of oscillation f_(max) of 60 GHz.At 10 GHz frequency and 20 V drain bias,the V-gate recess devices exhibited an output power density of 4.44 W/mm with the associated power added efficiency as high as 49%.     

A comparative study of wet and dry selective etching processes for GaAs/AIGaAs/lnGaAs pseudomorphic MODFETs

The etching characteristics of Al_xGa_1-xAs in citric acid/H₂O₂ solutions and SiCl₄/SiF₄ plasmas have been studied. Using a 4:1 solution of citric acid/H₂O₂ at 20° C, selectivities of 155, 260, and 1450 have been obtained for GaAs on Al_xGa_1-xAs withx = 0.3,x = 0.45, andx = 1.0, respectively. Etch rates of GaAs in this solution were found to be independent of line widths and crystal orientations for etched depths up to 1000?. GaAs etch profiles along [110] and [110] directions displayed different slope angles as expected. Selective reactive ion etching (SRIE) using SiCl₄/SiF₄ gas mixtures at 90 mTorr and -60 V self-biased voltage yielded selectivities between 200 and 500 forx values ranging from 0.17 to 1.0. SRIE etch rates for GaAs were relatively constant for etch depths of less than 1000?. At greater etch depths, etch rates varied by up to 76% for line widths between 0.3 and 1.0μm. Both selective wet etch and dry etch processes were applied to the fabrication of pseudomorphic GaAs/AIGaAs/lnGaAs MODFETs with gate lengths ranging from 0.3 to 2.5 μm on heterostructures with an embedded thin AlAs etch stop layer. A threshold voltage standard deviation of 13.5 mV for 0.3 μ gate-length MODFETs was achieved using a 4:1 citric acid/H₂O₂ solution for gate recessing. This result compares favorably with the 40 mV obtained using SRIE, and is much superior to the 230 mV achieved using the nonselective etch of 3:1:50 H₃PO₄: H₂O₂: H₂O. This shows that selective wet etching using citric acid/H₂O₂ solutions in conjunction with a thin Al_xGa_1-xAs(x ≥ 0.45) etch stop layer provides a reasonably simple, safe, and reliable process for gate recessing in the fabrication of pseudomorphic MODFETs.     

Polarization-Engineered Ga-Face GaN-Based Heterostructures for Normally-Off Heterostructure Field-Effect Transistors

Polarization-engineered Ga-face GaN-based heterostructures with a GaN cap layer and an AlGaN/p-GaN back barrier have been designed for normally-off field-effect transistors (FETs). The simulation results show that an unintentionally doped GaN cap and p-GaN layer in the buffer primarily deplete electrons in the channel and the Al_0.2Ga_0.8N back barrier helps to pinch off the channel. Experimentally, we have demonstrated a normally-off GaN-based field-effect transistor on the designed GaN cap/Al_0.3Ga_0.7N/GaN channel/Al_0.2Ga_0.8N/p-GaN/GaN heterostructure. A positive threshold voltage of 0.2 V and maximum transconductance of 2.6 mS/mm were achieved for 80-μm-long gate devices. The device fabrication process does not require a dry etching process for gate recessing, while highly selective etching of the GaN cap against a very thin Al_0.3GaN_0.7N top barrier has to be performed to create a two-dimensional electron gas for both the ohmic and access regions. A self-aligned, selective etch of the GaN cap in the access region is introduced, using the gate metal as an etch mask. The absence of gate recess etching is promising for uniform and repeatable threshold voltage control in normally-off AlGaN/GaN heterostructure FETs for power switching applications.     

Multi‐crystalline Si solar cells with very fast deposited (180 nm/min) passivating hot‐wire CVD silicon nitride as antireflection coating

Hot‐wire chemical vapor deposition (HWCVD) is a promising technique for very fast deposition of high quality thin films. We developed processing conditions for device‐ quality silicon nitride (a‐SiN_x:H) anti‐reflection coating (ARC) at high deposition rates of 3 nm/s. The HWCVD SiN_x layers were deposited on multicrystalline silicon (mc‐Si) solar cells provided by IMEC and ECN Solar Energy. Reference cells were provided with optimized parallel plate PECVD SiN_x and microwave PECVD SiN_x respectively. The application of HWCVD SiN_x on IMEC mc‐Si solar cells led to effective passivation, evidenced by a V_oc of 606 mV and consistent IQE curves. For further optimization, series were made with HW SiN_x (with different x) on mc‐Si solar cells from ECN Solar Energy. The best cell efficiencies were obtained for samples with a N/Si ratio of 1·2 and a high mass density of >2·9 g/cm³. The best solar cells reached an efficiency of 15·7%, which is similar to the best reference cell, made from neighboring wafers, with microwave PECVD SiN_x. The IQE measurements and high V_oc values for these cells with HW SiN_x demonstrate good bulk passivation. PC1D simulations confirm the excellent bulk‐ and surface‐passivation for HW SiN_x coatings. Interesting is the significantly higher blue response for the cells with HWCVD SiN_x when compared to the PECVD SiN_x reference cells. This difference in blue response is caused by lower light absorption of the HWCVD layers (compared to microwave CVD; ECN) and better surface passivation (compared to parallel plate PECVD; IMEC). The application of HW SiN_x as a passivating antireflection layer on mc‐Si solar cells leads to efficiencies comparable to those with optimized PECVD SiN_x coatings, although HWCVD is performed at a much higher deposition rate. Copyright © 2007 John Wiley & Sons, Ltd.     

栅槽刻蚀工艺对增强型GaN HEMT器件性能的影响

基于凹槽栅增强型氮化镓高电子迁移率晶体管(GaN HEMT)研究了不同的栅槽刻蚀工艺对GaN器件性能的影响。在栅槽刻蚀方面,采用了一种感应耦合等离子体(ICP)干法刻蚀技术与高温热氧化湿法刻蚀技术相结合的两步法刻蚀技术,将AlGaN势垒层全部刻蚀掉,制备出了阈值电压超过3 V的增强型Al_2O_3/AlGaN/GaN MIS-HEMT器件。相比于传统的ICP干法刻蚀技术,两步法是一种低损伤的自停止刻蚀技术,易于控制且具有高度可重复性,能够获得更高质量的刻蚀界面,所制备的器件增强型GaN MIS-HEMT器件具有阈值电压回滞小、电流开关比(I_ON/I_OFF)高、栅极泄漏电流小、击穿电压高等特性。     

Measuring stiffnesses and residual stresses of silicon nitride thin films

The mechanical deflection of circular membranes of SiN _x is presented as a technique for measuring the stiffness and residual stress of very thin, single-layer films. The dimensions of the membranes are controlled precisely using standard photolithography, dry etching and wet etching techniques. Thicknesses vary between 0.09 μm and 0.27 μm and average diameters range between 1100 μm and 4100 μm. A Nanoindenter is used to deflect the membranes with a point force at their centers, and to continuously record the applied forces and the resulting deflections. The analysis of the force-deflection data yields the values of Young’s moduli and residual stresses for the films.     

MetamorphicIn0.53Ga0.47As/In0.52Al0.48As HEMTs on germanium substrates

We report for the first time the successful epitaxial growth and processing of high-performance metamorphic high electron mobility transistors (HEMTs) on Ge substrates, with a transconductance of 700 mS/mm and a saturation channel current of 650 mA/mm. To reduce parasitic capacitances due to the conductive substrate, a dry etch method based on CF₄ and O₂ reactive ion etching (RIE) is developed for selective substrate removal. Devices with 0.2 μm gate length display an increase of the extrinsic cut-off frequency f_T from 45 GHz before, to 75 GHz after substrate removal, whereas the maximum oscillation frequency f_max increases from 68 GHz to 95 GHz. Based on this excellent rf performance level, in combination with the highly selective thinning process, we think that Ge as a sacrificial substrate is a promising candidate for the integration of thinned individual HEMTs with passive circuitry on low-cost substrates. This could result in low-cost advanced hybrid systems for mass-market millimeter wave applications     

先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀研究

研究了先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀工艺。对于poly-Si/TaN/HfSiON栅结构的刻蚀,我们采用的策略是对栅叠层中的每一层都进行高选择比地、陡直地刻蚀。首先,对于栅结构中poly-Si的刻蚀,开发了一种三步的等离子体刻蚀工艺,不仅得到了陡直的poly-Si刻蚀剖面而且该刻蚀可以可靠地停止在TaN金属栅上。然后,为了得到陡直的TaN刻蚀剖面,研究了多种BCl3基刻蚀气体对TaN金属栅的刻蚀,发现BCl3/Cl2/O2/Ar等离子体是合适的选择。而且,考虑到Cl2对Si衬底几乎没有选择比,采用优化的BCl3/Cl2/O2/Ar等离子体陡直地刻蚀掉TaN金属栅以后,我们采用BCl3/Ar等离子体刻蚀HfSiON高K介质,改善对Si衬底的选择比。最后,采用这些新的刻蚀工艺,成功地实现了poly-Si/TaN/HfSiON栅结构的刻蚀,该刻蚀不仅得到了陡直的刻蚀剖面且对Si衬底几乎没有损失。