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Seongjong Yoo Yongjoo Song Jiwoon Jung Myunghee Lee 《Journal of the Society for Information Display》2009,17(3):213-220
Abstract— A 12‐bit segmented R‐C DAC to support a linear gamma curve has been proposed and fabricated in a 720‐channel LCD source driver with a 16‐V 1‐poly 3‐metal high‐voltage CMOS process. The proposed DAC has a global resistor string and sample‐and‐hold buffers. A MSB voltage selected by the upper 6 bits of input data and a LSB voltage selected by the lower 6 bits of input data are summed by using a sample‐and‐hold operation with offset cancellation in the proposed DAC. The measured DNL was less than 0.3 LSB, and the output voltage deviation was less than 3 mV in all gray levels. Although two sample‐and‐hold buffers were adopted to operate alternatively, the die size was as small as 24.9 mm2, which was only an 8.3% increase compared to that of a conventional 8‐bit 720‐channel source driver. Because of its good performance with small area, the proposed DAC can be a good low‐cost solution for a 10‐bit TV system. 相似文献
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Hyeon‐Cheon Seol Seong‐Kwan Hong Oh‐Kyong Kwon 《Journal of the Society for Information Display》2017,25(1):4-11
A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/?0.52 least significant bit and +0.62/?0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one. 相似文献
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Yoo‐Chang Sung Oh‐Kyong Kwon Jong‐Kee Kim 《Journal of the Society for Information Display》2006,14(4):371-377
Abstract— A 10‐bit gray‐scale source driver using a resistor‐resistor‐string digital‐to‐analog converter (RR‐DAC) is proposed for a TFT‐LCD source driver. The 10‐bit RR‐DAC consists of an 8‐bit resistor‐string DAC and a two‐bit resistor‐string DAC without an intermediate unity‐gain buffer to isolate the parallel‐connected resistor string. The output deviation of the proposed source driver is less than ±3 mV. The chip area of the proposed 10‐bit source driver with an RR‐DAC is increased to 29% of that of an 8‐bit source driver. 相似文献
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C.C.Y. Liao Z‐H. Chen H.N.H. Cheng F‐C. Chen T‐W. Chan 《Journal of Computer Assisted Learning》2011,27(1):76-89
In the last decade, more and more games have been developed for handheld devices. Furthermore, the popularity of handheld devices and increase of wireless computing can be taken advantage of to provide students with more learning opportunities. Games also could bring promising benefits – specifically, motivating students to learn/play, sustaining their interest, reflecting their learning/playing status, and facilitating the learning/playing progress. However, most of these have been designed for entertainment rather than education. Hence, in this study we incorporate game elements into a learning environment. The My‐Mini‐Pet system is a handheld pet‐nurturing game environment, in which students learn with an animal learning companion, their My‐Mini‐Pet. Three design strategies are adopted. First, the pet‐nurturing strategy, which simulates the relationship between the pet and its owner, the My‐Mini‐Pet becomes a motivator/sustainer of learning. Second, the pet appearance‐changing strategy, which externalizes the learning status of the student. In other words, the My‐Mini‐Pet plays the role of a reflector. Third, the pet feedback strategy, which links the behaviours of the student and his/her pet, the My‐Mini‐Pet acts as a facilitator of learning. A pilot study was also conducted to preliminarily investigate the effectiveness and experiences of the strategies on allowing the student to understand arithmetic practices. The results showed that the strategy was effective, encouraging the students to engage in learning activities. Furthermore, the game attracted the students’ attention and stimulated discussion between peers. Some implications about the further developments are also discussed. 相似文献
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VXI总线四通道LVDS数据传输模块设计 总被引：1，自引：2，他引：1
针对国内测试系统开发中出现的低电压差分信号(LVDS)技术需求提出了一种VXI总线四通道LVDS数据传输模块的设计实现方法;以FPGA作为控制核心,利用Verilog HDL设计实现了VXI接口和HDLC通讯协议设计,并通过基于VXI总线的块传输方式和乒乓存储技术,完成了大批量数据的接收;另外,为确保LVDS信号的完整性,结合实际设计和调试经验,文中还分析了LVDS接口信号印制板布线和布局问题;该模块已用于测试系统开发,并实现了测试系统与被测设备的视频信号传输;应用结果表明,模块传输速度为4Mbit/s时误码率小于10-6。 相似文献
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自举系统在并行系统研发中占有重要地位.在分析和比较单DSP自举原理的基础上,设计并实现了一种应用在多处理器平台的混合模式自举系统.该系统采用嵌套架构结合EPROM和链路口这两种加载模式,成功实现了单Flash芯片引导多处理器问的不同应用程序.与单一模式的EPROM自举系统相比,降低开发成本.减少功耗,提高了系统的可靠性和扩展性,为多DSP的大规模集成提供了广阔的应用前景. 相似文献
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本文介绍了一种利用PC机设备来设计模拟信号发生器的方案。该方案通过利用PC机内的充分资源来产生各种所需波形,然后通过USB2.0接口输出。在PC机外采用DAC8580对数字信号进行DA转换,并用CPLD对整个电路进行控制。 相似文献
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潘未庄 《单片机与嵌入式系统应用》2009,(4):15-17
简要分析sigma—delta（∑-△）架构模数转换器（ADC）原理,提出一种基于FPGA内部LVDS（Low Voltage Differential Signaling）接收器的音频ADC架构,并给出在FPGA上的实现结果。在FPGA内部实现音频ADC,具有扩展方便灵活,实现简单,集成度高等优点。 相似文献
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针对遥测系统远程数据传输过程中出现的由于干扰引起的误操作以及数据紊乱问题,提出了一种基于LVDS的具有高可靠性的通信系统解决方案;系统以FPGA为控制核心,采用LVDS高速数据传输技术,实现飞行器遥测数据存储系统与地面设备的通信;为保证数据链路与命令控制链路的准确性和可靠性,设计了一套完整的通信协议;经大量试验表明,该通信系统性能稳定、数据及命令传输可靠,现已应用于某航天遥测数据通信系统. 相似文献
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Soo Hwan Kim Hyunwoo Park Suki Kim Richard McCartney 《Journal of the Society for Information Display》2006,14(4):379-386
Abstract— The row‐line and data‐line that make up of a TFT‐LCD panel can be modeled as a distributed resistance and capacitance network. As TFT‐LCD panels become larger and provide higher resolution, the induced signal propagation delay time from the row and column lines become an appreciable part of the line time. In particular, the row signal‐propagation delay time is traditionally accommodated by waiting for the worst‐case propagation time before the start of a new line. This conventional method, however, reduces the subpixel charging time. A new driving method, Horizontal Line Delay Compensation (H‐LDC), has been implemented and verified to compensate for row‐line propagation delay. The benefit of longer subpixel charging time is of particular interest to large‐area high‐resolution fast‐refresh‐rate LCD TVs. 相似文献
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主要介绍以ARM Mini2440嵌入式开发板为核心,在移动设备中实现多种文件系统的硬件电路结构和软件实现方法。本系统是以ARM Mini2440系列开发板为主控制器,通过对USB接口的控制,从而可以对移动设备里面的多种格式的文件进行复制、粘贴、显示等操作,并通过触摸显示屏可以显示移动设备中部分格式文件的内容。经过实验测试,本系统能可靠地对移动设备中的文件进行读写和转移等操作。 相似文献
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针对测控系统中,对数据传输速度和稳定性要求越来越高的现状,提出结合串行通信标准LVDS技术和串行通讯协议SPI,完成一种高速数据通信板卡的设计与开发;板卡采用ALTERA公司生产的EP3C16Q240C8这款FPGA完成,并在ALTERA公司提供的QuartusII软件支持下进行了编程和仿真;板卡的电路设计原理清晰、工作可靠,已经应用于测控系统中;经测试,该板卡可将高达200Mhz的数据传输3米,为高速测试设备的研制开发提供了可行的解决方案。 相似文献
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提出了一种通过FPGA实现PCI-Express(简称PCIE)接口卡的方法,对LVDS信号以及PCIE接口技术进行了充分的研究,设计未采用FPGA自带的PCIE硬核,而是根据PCIE总线桥接芯片对接口时序直接控制,最大程度优化接口逻辑,提高接口传输速率和稳定性;试验中LVDS器件接收LVDS总线上大小为513(列)*512(行)*8(位)的渐变图像,像素时钟为15MHz,帧频率为10帧/s,并传输到FPGA控制部分,FPGA控制部分向PCIE接口发送中断并完成图像数据上传;文中详细讨论了不同模块的实现原理,完成了实际测试和分析,测试结果表明该设计性能稳定,可以实现PCIE接口卡高速数据通信。 相似文献
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介绍了D／A转换芯片DAC7625和电压／电流转换芯片XTR110的原理及应用，采用DAC7625和XTR110，设计了一种DSP系统的模拟量输出接口。 相似文献