A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.     

16‐QAM OFDM‐Based W‐Band Polarization‐Division Duplex Communication System with Multi‐gigabit Performance

This paper presents a novel 90 GHz band 16‐quadrature amplitude modulation (16‐QAM) orthogonal frequency‐division multiplexing (OFDM) communication system. The system can deliver 6 Gbps through six channels with a bandwidth of 3 GHz. Each channel occupies 500 MHz and delivers 1 Gbps using 16‐QAM OFDM. To implement the system, a low‐noise amplifier and an RF up/down conversion fourth‐harmonically pumped mixer are implemented using a 0.1‐μm gallium arsenide pseudomorphic high‐electron‐mobility transistor process. A polarization‐division duplex architecture is used for full‐duplex communication. In a digital modem, OFDM with 256‐point fast Fourier transform and (255, 239) Reed‐Solomon forward error correction codecs are used. The modem can compensate for a carrier‐frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of 10^–5 at a signal‐to‐noise ratio of about 19.8 dB.     

High‐Speed Access over Copper: Rate Optimization and Signal Construction

This paper focuses on assessment and design of transmission systems for distribution of digital signals over standard Category‐7A copper cables at speeds beyond 10 Gbps. The main contribution of this paper is on the technical feasibility and system design for data rates of 40 Gbps and 100 Gbps over copper. Based on capacity analysis and rate optimization algorithms, system parameters are obtained and the design implementation trade‐offs are discussed. Our simulation results confirm that with the aid of a decision‐feedback equalizer and powerful coding techniques, namely, TCM or LDPC code, 40 Gbps transmission is feasible over 50 m of CAT‐7A copper cable. These results also indicate that 100 Gbps transmission can be achieved over 15 m cables.     

40 Gbps All‐Optical 3R Regeneration and Format Conversion with Related InP‐Based Semiconductor Devices

We report an experimental demonstration of 40 Gbps all‐optical 3R regeneration with all‐optical clock recovery based on InP semiconductor devices. We also obtain all optical non‐return‐to‐zero to return‐to‐zero (NRZ‐to‐RZ) format conversion using the recovered clock signal at 10 Gbps and 40 Gbps. It leads to a good performance using a Mach‐Zehnder interferometric wavelength converter and a self‐pulsating laser diode (LD). The self‐pulsating LD serves a recovered clock, which has an rms timing jitter as low as sub‐picosecond. In the case of 3R regeneration of RZ data, we achieve a 1.0 dB power penalty at 10^?9 BER after demultiplexing 40 Gbps to 10 Gbps with an eletro‐absorption modulator. The regenerated 3R data shows stable error‐free operation with no BER floor for all channels. The combination of these functional devices provides all‐optical 3R regeneration with NRZ‐to‐RZ conversion.     

The Effect of Gate‐Dielectric Surface Energy on Pentacene Morphology and Organic Field‐Effect Transistor Characteristics

The effects of the surface energy of polymer gate dielectrics on pentacene morphology and the electrical properties of pentacene field‐effect transistors (FETs) are reported, using surface‐energy‐controllable poly(imide‐siloxane)s as gate‐dielectric layers. The surface energy of gate dielectrics strongly influences the pentacene film morphology and growth mode, producing Stranski–Krastanov growth with large and dendritic grains at high surface energy and three‐dimensional island growth with small grains at low surface energy. In spite of the small grain size (≈ 300 nm) and decreased ordering of pentacene molecules vertical to the gate dielectric with low surface energy, the mobility of FETs with a low‐surface‐energy gate dielectric is larger by a factor of about five, compared to their high‐surface‐energy counterparts. In pentacene growth on the low‐surface‐energy gate dielectric, interconnection between grains is observed and gradual lateral growth of grains causes the vacant space between grains to be filled. Hence, the higher mobility of the FETs with low‐surface‐energy gate dielectrics can be achieved by interconnection and tight packing between pentacene grains. On the other hand, the high‐surface‐energy dielectric forms the first pentacene layer with some voids and then successive, incomplete layers over the first, which can limit the transport of charge carriers and cause lower carrier mobility, in spite of the formation of large grains (≈ 1.3 μm) in a thicker pentacene film.     

Optoelectronic In‐Ga‐Zn‐O Memtransistors for Artificial Vision System

An artificial vision system that can simulate the visual functions of human eyes is required for biological robots. Here, In‐Ga‐Zn‐O memtransistors using a naturally oxidized Al₂O₃ and an ion gel as a common gate stacking dielectric is proposed. Positive charge trapping in the Al₂O₃ layer can be induced by modulating the gate voltage, which causes the back sweep subthreshold swing (SS) of the device to break the physical limit (≥60 mV per decade at room temperature), and the minimum SS is as low as 26.4 mV per decade. In addition, photogenerated charges in the device are captured at the In‐Ga‐Zn‐O channel/ion gel interface due to the superposition of the additional electric field generated by positive charges trapped in the Al₂O₃ layer and the external gate electric field. Thus, persistent photoconductivity is observed in the In‐Ga‐Zn‐O memtransistors. Finally, by employing the optoelectronic memristive functions of In‐Ga‐Zn‐O memtransistors, an artificial vision system based on artificial retinal array (ARA) and artificial neural network is proposed. An obvious improvement in the recognition rate and efficiency with the use of ARA for the image preprocessing is achieved. This study provides a new strategy for the realization of artificial vision systems.     

16‐QAM‐Based Highly Spectral‐Efficient E‐band Communication System with Bit Rate up to 10 Gbps

This paper presents a novel 16‐quadrature‐amplitude‐modulation (QAM) E‐band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71‐76 GHz/81‐86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16‐QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up‐/down‐conversion mixer are implemented using a 0.1 µm gallium arsenide pseudomorphic high‐electron‐mobility transistor (GaAs pHEMT) process. A single‐IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed‐Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier‐frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of 10^?5 at a signal‐to‐noise ratio of about 21.5 dB.     

A CMOS 5.4/3.24‐Gbps Dual‐Rate CDR with Enhanced Quarter‐Rate Linear Phase Detector

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter‐rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead‐zone problem of charge pump circuit. A voltage‐controlled oscillator is designed with a ‘Mode’ switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak‐to‐peak jitter is 24.89 ps under 231–1 bit‐long pseudo‐random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm×1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 μm CMOS process.     

Signal integrity analysis of system interconnection module of high‐density server supporting serial RapidIO

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high‐density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack‐up types on a printed circuit board. Each module was designed into 12‐ (version 1) and 14‐layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high‐speed signal‐layers in the middle of two power planes, whereas Version 2 has a single high‐speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S‐parameters, eye‐diagrams, and crosstalk voltages. The results show that the high‐speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.     

Organic Junction Field‐Effect Transistor

The realization and performance of a novel organic field‐effect transistor—the organic junction field‐effect transistor (JFET)—is discussed. The transistors are based on the modulation of the thickness of a depletion layer in an organic pin junction with varying gate potential. Based on numerical modeling, suitable layer thicknesses and doping concentrations are identified. Experimentally, organic JFETs are realized and it is shown that the devices clearly exhibit amplification. Changes in the electrical characteristics due to a variation of the intrinsic and the p‐doped layer thickness are rationalized by the numerical model, giving further proof to the proposed operational mechanism.     

An FPGA Implementation of High‐Speed Flexible 27‐Mbps 8‐StateTurbo Decoder

In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half‐rate turbo decoder designed for binary quadrature phase‐shift keying (B/QPSK) modulation. A transformation applied to the incoming I‐channel and Q‐channel symbols allows the use of an off‐the‐shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix‐4, dual‐path processing, parallel decoding, and early‐stop algorithms. We implement the proposed scheme on a field‐programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.     

Design and Experiment Results of High‐Speed Wireless Link Using Sub‐terahertz Wave Generated by Photonics‐Based Technology

Using a sub‐terahertz (sub‐THz) wave generated using a photonics‐based technology, a high‐speed wireless link operating at up to 10 Gbps is designed and demonstrated for realization of seamless connectivity between wireless and wired networks. The sub‐THz region is focused upon because of the possibility to obtain sufficient bandwidth without interference with the allocated RF bands. To verify the high‐speed wireless link, such dynamic characteristics as the eye diagrams and bit error rate (BER) are measured at up to 10 Gbps for non‐return‐to‐zero pseudorandom binary sequence data. From the measurement results, a receiver sensitivity of –23.5 dBm at is observed without any error corrections when the link distance between the transmitter and receiver is 3 m. Consequently, we hope that our design and experiment results will be helpful in implementing a high‐speed wireless link using a sub‐THz wave.     

Performance of wavelet based Multi‐Chip Rate DS‐CDMA signals over multi‐path Nakagami‐m fading channels

Multi‐Chip Rate/Direct Sequence‐Code Division Multiple Access (MCR/DS‐CDMA) technique using scaled chip waveforms has been designed as an alternative to multi‐data rate DS‐CDMA techniques having constant chip rates. In this work, the probability of error (P_e) expression for MCR/DS‐CDMA signals is derived over multi‐path Nakagami‐m fading channels to investigate the effects of chip waveforms on it. This paper also proposes the use of orthogonal wavelets as chip waveforms of MCR/DS‐CDMA signals over the considered channel. For numerical calculations, Daubechies‐22 (D₂₂) wavelet is used because its side lobes are 40 dB below its main lobe in frequency domain. D₂₂ is compared with a Square Root Raised Cosine (SRRC) chip waveform. In the numerical calculations, only first four scales of the chip waveforms relating to four different chip/data rates are considered. The results for the P_e performance and the capacity (the number of user per Hertz for a same P_e level) show that D₂₂ significantly outperforms the SRRC chip waveform at all data rates, due to low cross correlations among different scales of orthogonal wavelets. Besides, by increasing the number of scales, the advantage of the use of orthogonal wavelets will increase furthermore. Copyright © 2007 John Wiley & Sons, Ltd.     

10 Gbps Optical Signal Transmission via Long‐Range Surface Plasmon Polariton Waveguide

We demonstrate 10 Gbps optical signal transmission via long‐range surface plasmon polaritons (LR‐SPPs) in a very thin metal strip‐guided geometry. The LR‐SPP waveguide was fabricated as a 14 nm thick, 2.5 μm wide, and 4 cm long gold strip embedded in a polymer and pigtailed with single‐mode fibers. The total insertion loss of 16 dB was achieved at a wavelength of 1.55 μm as a carrier wave. In a 10 Gbps optical signal transmission experiment, the LR‐SPP waveguide exhibits an excellent eye opening and a 2.2 dB power penalty at 10^?12 bit error rate. We confirm, for the first time, that LR‐SPPs can efficiently transfer data signals as well as the carrier light.     

Demonstration of CSRZ Signal Generator Using Single‐Stage Mach‐Zehnder Modulator and Wideband CMOS Signal Mixer

In this paper, we demonstrate an electrically band‐limited carrier‐suppressed return‐to‐zero (EB‐CSRZ) signal generator operating up to a 10 Gbps data rate comprising a single‐stage Mach‐Zehnder modulator and a wideband signal mixer. The wideband signal mixer comprises inverter stages, a mixing stage, and a gain amplifier. It is implemented by using a 0.13 μm CMOS technology. Its transmission response shows a frequency range from DC to 6.4 GHz, and the isolation response between data and clock signals is about 21 dB at 6.4 GHz. Experimental results show optical spectral narrowing due to incorporating an electrical band‐limiting filter and some waveform distortion due to bandwidth limitation by the filter. At 10 Gbps transmission, the chromatic dispersion tolerance of the EB‐CSRZ signal is better than that of NRZ‐modulated signal in single‐mode fiber.     

Gate Capacitance‐Dependent Field‐Effect Mobility in Solution‐Processed Oxide Semiconductor Thin‐Film Transistors

Solution‐processed oxide semiconductors (OSs) used as channel layer have been presented as a solution to the demand for flexible, cheap, and transparent thin‐film transistors (TFTs). In order to produce high‐performance and long‐sustainable portable devices with the solution‐processed OS TFTs, the low‐operational voltage driving current is a key issue. Experimentally, increasing the gate‐insulator capacitances by high‐k dielectrics in the OS TFTs has significantly improved the field‐effect mobility of the OS TFTs. But, methodical examinations of how the field‐effect mobility depends on gate capacitance have not been presented yet. Here, a systematic analysis of the field‐effect mobility on the gate capacitances in the solution‐processed OS TFTs is presented, where the multiple‐trapping‐and‐release and hopping percolation mechanism are used to describe the electrical conductivity of the nanocrystalline and amorphous OSs, respectively. An intuitive single‐piece expression showing how the field‐effect mobility depends on gate capacitance is developed based on the aforementioned mechanisms. The field‐effect mobility, depending on the gate capacitances, of the fabricated ZnO and ZnSnO TFTs clearly follows the theoretical prediction. In addition, the way in which the gate insulator properties (e.g., gate capacitance or dielectric constant) affect the field‐effect mobility maximum in the nanocrystalline ZnO and amorphous ZnSnO TFTs are investigated.     

Design Space Exploration for NoC‐Style Bus Networks

With the number of IP cores in a multicore system‐on‐chip increasing to up to tens or hundreds, the role of on‐chip interconnection networks is vital. We propose a networks‐on‐chip‐style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade‐off for the time saving, the time cost (TC) of the searched architecture is increased to up to and , respectively, at each step compared with that of the architecture obtained through full‐case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to when compared with that obtained through full‐case exploration.     

Feed‐Forward Control of Transient Gain Dynamics of an EDFA for Optical Burst Networks

In this letter, we demonstrate a technique for suppression of transients in output bursts of an erbium‐doped fiber amplifier (EDFA) in an optical burst network. To suppress the transients, the EDFA is forward‐fed by non‐fluctuating input utilizing a power‐modulated burst control packet channel. Using the technique, we obtained a maximum 1.7 dB reduction in gain transient in the EDFA output, and we transmitted 9.953 Gbps data bursts and 2.488 Gbps burst control packets stably.     

New Path‐Setup Method for Optical Network‐on‐Chip

With high bandwidth, low interference, and low power consumption, optical network‐on‐chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path‐setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non‐blocking optical router is designed to support the new method. The simulation results show the new path‐setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot‐I, and hotspot‐II traffic patterns, respectively. The end‐to‐end delay performance is also improved.     

Prediction of triple‐orbital diversity performance in Earth‐space communication

Orbital diversity is considered to be an effective technique to overcome large fade margins in satellite communication links. This paper discusses triple‐orbital diversity, which uses three satellites and an Earth receiving site. A method for calculating the outage probability of a triple‐orbital diversity protection scheme is proposed. It is based on a model for convective raincells and the lognormal assumption for point rainfall rate statistics. Numerical results are compared with an available set of experimental data taken from a VSAT Earth‐station located in Japan. The agreement was found to be quite encouraging. Some useful conclusions, concerning the relative advantage of using triple‐ against the double‐orbital diversity scheme are also deduced. Copyright © 2002 John Wiley & Sons, Ltd.