On Combining Chase‐2 and Sum‐Product Algorithms for LDPC Codes

This letter investigates the combination of the Chase‐2 and sum‐product (SP) algorithms for low‐density parity‐check (LDPC) codes. A simple modification of the tanh rule for check node update is given, which incorporates test error patterns (TEPs) used in the Chase algorithm into SP decoding of LDPC codes. Moreover, a simple yet effective approach is proposed to construct TEPs for dealing with decoding failures with low‐weight syndromes. Simulation results show that the proposed algorithm is effective in improving both the waterfall and error floor performance of LDPC codes.     

基于自身可信度的低复杂度LDPC码位翻转解码算法

提出一种基于位翻转的低复杂度、便于硬件实现的LDPC码解码算法.该算法充分利用变量节点的本征信息来计算翻转判决函数,减少了对其它变量节点软信息的需求,因此大大降低了解码硬件实现的复杂度,同时保证翻转判决函数具有较高的可靠性.利用该算法,对RS-based LDPC码进行的仿真结果表明,改进算法的解码性能接近甚至略优于IMWBF算法.     

准循环LDPC码的半并行译码器设计

利用准循环LDPC码的结构特点,使用半并行结构的译码器可以实现复杂度和译码速率的有效折中.提出了一种半并行结构的实现方法,并通过FPGA上的实现验证了性能.     

非规则全分集LDPC码的构造方法

提出一种基于渐进边增长（Progressive Edge．Growth,PEG）算法的非规则全分集低密度奇偶校验（Low—Density Parity—Check,LDPC）码的构造方法。首先根据度分布和码率,对非规则全分集LDPC码中的节点进行度分配;然后对PEG算法中校验节点的选择标准加以约束,生成消除短环的非规则全分集LDPC码;进一步,通过改变局部校验节点剩余度的方法,解决在特殊度分布下算法失效的问题。仿真结果表明,构造的非规则全分集LDPC码在瑞利块衰落信道下能够实现全分集;在码长、码率相同的情况下与规则全分集LDPC码相比,非规则全分集LD—PC码能够获得更高的编码增益。     

基于LDPC码的OFDM系统性能分析

正交频分复用(OFDM)是一种多载波调制技术,已成为实现高速数据传输的主流技术,在无线局域网、HDTV中得到广泛应用;低密度奇偶校验(LDPC)码是一种译码复杂度低的纠错码,可获得接近香农限的优异性能。本文提出了结合LDPC码的COFDM系统方案,阐述了相关原理,对其性能进行了仿真分析,比较了在不同调制方法下系统的性能差异,并将基于LDPC码和Turbo码的COFDM系统在不同信道中的误码性能进行了对比。仿真结果表明,基于LDPC码的COFDM系统在提供较高比特传输速率的同时也具有良好的纠错性能。     

LDPC码和-积解码算法研究

首先介绍了LDPC 码的校验矩阵和其因子表示方法,然后利用二分图对和积解码算法进行了详细的描述,最后给出了信度传播概率译码算法详细步骤,并对关键公式作了证明。     

基于FPGA的不可分层LDPC码译码器

针对不可分层LDPC码无法采用分层译码算法的问题,设计了一种新型的LDPC码分层译码器。与传统分层译码器的结构不同,新结构在各层间进行并行更新,各层内进行串行更新。通过保证在不同分层的同一变量节点不同时进行更新,达到分层译码算法分层递进更新的目标。选用Altera公司的CycloneⅢ系列EP3C120器件,实现码率3/4,码长8 192的(3,12)规则不可分层QC-LDPC码译码器的布局布线,在最大迭代次数为5次时,最高时钟频率可以达到45.44 MHz,吞吐量可以达到47.6 Mbps。     

光通信系统中LDPC码的构造及其编译码算法分析

针对低密度奇偶校验（LDPC）码的相关理论和LDPC码自身特性以及光通信系统具有低噪声、高信噪比的传输特点进行分析后,提出了光通信系统中LDPC码型的构造方法,这为光通信系统中LDPC码型的构造和仿真分析奠定了基础。并对光通信系统中LDPC码的编译码算法进行了深入分析与研究,得到一些有利于降低其编译码算法复杂度的重要结论,这有助于降低其编译码器的设计与实现复杂度。     

一种估测LDPC码最小距离的方法

由于LDPC码具有译码复杂度低,纠错性能好等众多优点,WiMAX 802.16e标准已将 LDPC 码作为OFDMA物理层的一种信道编码方案.本文采用从最小距离和码重分布的角度来研究LDPC码的纠错性能,深入研究了估计LDPC码距离特性的ANC算法,并利用此算法估测出几组LDPC码的最小距离.结果验证了ANC算法的正确...     

LDPC码的信道自适应迭代译码算法

中短长度LDPC码采用BP迭代译码时,在低信噪比区,大量的经过多次迭代仍不能纠正的错误帧造成了平均迭代次数的大大增加;在中高信噪比区,比特对数似然比值的振荡造成了译码性能的降低。为了减少低信噪比区的平均迭代次数,提高中高信噪比区的译码性能,本文提出了一种LDPC码的信道自适应迭代译码算法。该算法采用基于校验和错误模式的预判决机制和消息加权平均算法,通过低信噪比区预判决机制的主导作用来减少平均迭代次数,通过中高信噪比区消息加权平均算法的主导作用来抑制因比特LLR值振荡而形成的错误帧,从而实现译码算法与信道变化特征的自适应,提高了译码效率。仿真结果显示,相对于BP译码算法,该译码算法在低信噪比区减少了平均迭代次数而译码性能没有显著变化,在中高信噪比区提高了译码性能而平均迭代次数没有明显增加。     

低密度校验码量化译码研究

介绍了基于置信传播算法的LDPC码和积译码算法，分析其密度进行化特性，对不同消息空间中的量化译码问题进行研究，对采用不同量化方案时LDPC码在AWGN信道下的译码性能进行了仿真。仿真结果表明相对连续译码，中间变量6bit均匀量化会带来约0．4dB左右的损失，而10bit非均匀量化性能明显得到改善。合适的高阶量化译码可以获得接近连续译码的性能。     

DVB-S2标准LDPC码的算法研究和仿真

阐述了LDPC(Low Density Parity Check)码的基本原理,基于DVB-S2中LDPC码分析了该类码的构造、编码及译码原理,同时给出DVB-S2中LDPC码在码率为2/3、码长为16200bits时的仿真结果。仿真结果表明,在低信噪比情况下,该LDPC码仍然获得了令人满意的纠错效果,且在性能上的确优于其他码。随着技术的进步,相信LDPC编译码技术将在更多的领域得到应用。     

多进制LDPC译码算法的研究

多进制LDPC码是将二进制LDPC码推广到有限域GF（q）,其校验矩阵的元素不再是（0,1）,而是集合（0,1,…,q-1）,译码仍然采用高效的基于置信度传播的迭代译码算法。这里主要推导了多进制译码算法的迭代公式,分析证明了基于快速傅里叶变换（FFT）理论的改进算法,最后通过仿真手段验证和分析了基于FFT的多进制译码算法的优越性能。     

Design of Encoder and Decoder for LDPC Codes Using Hybrid H‐Matrix

Low‐density parity‐check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H‐matrices are constructed so that both the semi‐random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog‐HDL and are synthesized using a 0.35 µm CMOS standard cell library.     

DVB-S2标准 LDPC码的算法研究和仿真

阐述了LDPC（Low Density Parity Check）码的基本原理，基于DVB—S2中LDPC码分析了该类码的构造、编码及译码原理，同时给出DVB—S2中LDPC码在码率为2／3、码长为16200bits时的仿真结果。仿真结果表明，在低信噪比情况下，该LDPC码仍然获得了令人满意的纠错效果，且在性能上的确优于其他码。随着技术的进步，相信LDPC编译码技术将在更多的领域得到应用。     

一种简化的LDPC码BP译码算法的研究

低密度奇偶校验码(LDPC码)是一种逼近香农限的线性分组码,译码的复杂度较低;在LDPC码译码算法中性能较好的是置信传播译码(BP)算法,他能够在迭代译码过程中确定码字是否已译出,但是复杂度高,运算量大。采用一种改进的BP译码算法,在迭代译码过程中对校验节点的更新信息进行曲线拟合,以减小译码运算量,有利于硬件的并行实现,减少译码延时。仿真结果表明,改进的BP算法译码性能和原来的BP算法接近,而且复杂度较低。     

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm² programmable decoder core for a rate-1/2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power.Mohammad M. Mansour received his B.E. degree with distinction in 1996 and his M.S. degree in 1998 all in Computer and Communications Engineering from the American University of Beirut (AUB). In August 2002, he received his M.S. degree in Mathematics from the University of Illinois at Urbana-Champaign (UIUC). Mohammad received his Ph.D. in Electrical Engineering in May 2003 from UIUC. He is currently an Assistant Professor of Electrical Engineering with the ECE department at AUB. From 1998 to 2003, he was a research assistant at the Coordinated Science Laboratory (CSL) at UIUC. In 1997 he was a research assistant at the ECE department at AUB, and in 1996 he was a teaching assistant at the same department. From 1992–1996 he was on the Deans honor list at AUB. He received the Harriri Foundation award twice in 1996 and 1998, the Charli S. Korban award twice in 1996 and 1998, the Makhzoumi Foundation Award in 1998, and the PHI Kappa PHI Honor Society awards in 2000 and 2001. During the summer of 2000, he worked at National Semiconductor Corp., San Francisco, CA, with the wireless research group. His research interests are VLSI architectures and integrated circuit (IC) design for communications and coding theory applications, digital signal processing systems and general purpose computing systems.Naresh R. Shanbhag received the B.Tech from the Indian Institute of Technology, New Delhi, India, in 1988, M.S. from Wright State University and Ph.D. degree from the University of Minnesota, in 1993, all in Electrical Engineering. From July 1993 to August 1995, he worked at AT&T Bell Laboratories at Murray Hill in the Wide-Area Networks Group, where he was responsible of development of VLSI algorithms, architectures and implementation for high-speed data communications applications. In particular, he was the lead chip architect for AT&Ts 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and broadband access. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently an Associate Professor and Director of the Illinois Center for Integrated Microsystems. At University of Illinois, he founded the VLSI Information Processing Systems (ViPS) Group, whose charter is to explore issues related to low-power, high-performance, and reliable integrated circuit implementations of broadband communications and digital signal processing systems. He has published numerous journal articles/book chapters/conference publications in this area and holds three US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters (Norwell, MA: Kluwer, 1994). Dr. Shanbhag received the 2001 IEEE Transactions Best Paper Award, 1999 Xerox Faculty Research Award, 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1997 Distinguished Lecturer of IEEE Circuit and Systems Society (97–99), the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems society. From 1997–99 and 2000–2002, he served as an Associate Editor for IEEE Transaction on Circuits and Systems: Part II and an Associate Editor for the IEEE Transactions on VLSI, respectively. He was the technical program chair for the 2002 IEEE Workshop on Signal Processing Systems (SiPS02).     

LDPC码的不等误差保护性能研究

非规则LDPC(low-density parity-check)码具有不等误差保护性能,但是随机编码过程却使这一特性很难实现.现将PEG(Progressive Edge-Growth)算法与信道编码的UEP(Unequal Error Protection)性能相结合,用于构造具有不等误差保护性能的校验矩阵H.AWGN和Rayleigh信道的仿真结果表明,采用PEG算法构造的具有UEP性能的非规则LDPC码能够有效提高系统性能.     

一种优化LDPC码环分布的改进算法

在下一代移动通信系统中,为了满足移动用户对高速、宽带数据传输业务不断增长和更高质量的要求,需要对现有物理层的关键技术作进一步的改进、完善和实用化,例如在信道编码方面,就采用了革命性的LDPC码。而PEG算法则是目前构造中短码长LDPC码最有效的算法之一。通过借鉴ACE算法,在对已有的结构优化设计算法深入理解的基础上,对PEG算法进行了改进,得到了一种可以进一步优化LDPC码环分布和最小距离的改进算法。仿真结果表明：由新算法构造出来的LDPC码的环分布和码重分布都明显优于PEG算法;其性能曲线在低信噪比时与原算法相差不大,而随着信噪比的增加可以有效地降低错误平层。     

在BIAWGN信道下规则LDPC码的设计与仿真分析

LDPC码是一种逼近香农限 ,实现容易 ,系统复杂度低的优秀的线性纠错码。奇偶校验矩阵 H是决定一个 LDPC码性能的关键。本文针对规则 LDPC码 ,提出了两种随机构造 H的方式 :行列都均匀的 evenboth和仅列均匀的 evencol。通过仿真分析发现 ,由 evenboth方式生成的规则 LDPC码性能更好。本文还对规则 LDPC码与卷积码的性能进行了对比 ,证明了规则 LDPC码在中短帧传输下的优异性能。这对 LDPC码投入实际应用具有重要的意义