Performance Analysis for MPEG‐4 Video Codec Based on On‐Chip Network

In this paper, we present a performance analysis for an MPEG‐4 video codec based on the on‐chip network communication architecture. The existing on‐chip buses of system‐on‐a‐chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on‐chip network is introduced to solve the problem of on‐chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG‐4 video codec based on the on‐chip network and Advanced Micro‐controller Bus Architecture (AMBA) on‐chip bus. Experimental results show that the performance of the MPEG‐4 video codec based on the on‐chip network is improved over 50% compared to the design based on a multi‐layer AMBA bus.     

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

This paper presents an 8×8 bit pipelined multiplier operating at 320 MHz under 0.5 V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5 V. The proposed pipelined multiplier is fabricated in 130 nm CMOS process. It operates up to 320 MHz and the power consumption is only 1.48 mW at 0.5 V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5 V is reduced over 5.7 times than that of the traditional architecture at 1.2 V. Thus, the proposed 8×8 bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.     

A Platform‐Based SoC Design of a 32‐Bit Smart Card

In this paper, we describe the development of a platform‐based SoC of a 32‐bit smart card. The smart card uses a 32‐bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 µm technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.     

VLSI Implementation of H.264 Video Decoder for Mobile Multimedia Application

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A‐MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system‐on‐a‐chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is 7.5 mm×7.5 mm (using 0.25 micron 4‐layers metal CMOS technology).     

Automated performance‐based design technique for an efficient LTE PDSCH implementation using SDSoC tool

System on a chip (SoC) creates massive design challenges for SoC‐based designers. The design challenges start from functional, architectural verification complexity and finally meeting performance constraints. In addition, heterogeneity of components and tools introduces long design cycles. The Software‐Defined System‐on‐Chip (SDSoC) developed by Xilinx is used to create custom SoC on a heterogeneous FPGA‐CPU platform. The SDSoC tool provides fast, flexible, and short design cycle to develop heterogeneous FPGA‐CPU platform. The objective of this paper is to introduce a new automated design technique to build a SoC on a heterogeneous FPGA‐CPU platform that meets design requirements using SDSoC tool. In this paper, the typical SDSoC design flow is introduced. In addition, a new automated SDSoC design technique is developed to design SoC on a heterogeneous FPGA‐CPU platform on the basis of performance metrics such as area, power, and latency. Design of physical downlink shared channel (PDSCH) in long‐term evolution (LTE) is presented as a case study. This paper provides the implementation of the transmitter and the receiver of the PDSCH in LTE using SDSoC tool and selects a platform that meets performance metrics constraints.     

Test Scheduling of NoC‐Based SoCs Using Multiple Test Clocks

Network‐on‐chip (NoC) is an emerging design paradigm intended to cope with future systems‐on‐chips (SoCs) containing numerous built‐in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC‐based SoCs. Among the existing test issues for NoC‐based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC‐based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC‐based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC‐based SoCs.     

ARTS: A SystemC-based framework for multiprocessor Systems-on-Chip modelling

One of the challenges of designing a heterogeneous multiprocessor SoC is to find the right partitioning of the application for the target platform architecture. The right partitioning is dependent on the characteristics of the processors and the network connecting them as well as the application. We present an abstract system-level modelling and simulation framework (ARTS) which allows for cross-layer modelling and analysis covering the application layer, middleware layer, and hardware layer. ARTS allows MPSoC designers to explore and analyze the network performance under different traffic and load conditions, consequences of different task mappings to processors (software or hardware) including memory and power usage, and effects of RTOS selection, including scheduling, synchronization and resource allocation policies. We present the application and platform models of ARTS as well as their implementation in SystemC. We present the usage of the ARTS framework as seen from platform developers’ point of view, where new components may be created and integrated into the framework, and from application designers’ point of view, where existing components are used to explore possible implementations. The latter is illustrated through a case study of a real-time, smart phone application consisting of 5 applications with a total of 114 tasks mapped onto different platforms. Finally, we discuss the simulation performance of the ARTS framework in relation to scalability. This work has been partially funded by ARTIST2 (IST-004527).     

使用SystemC设计片上自演化系统

提出片上自演化系统的概念和基于SystemC的片上自演化系统设计方法,给出片上自演化系统的总体结构,使用SystemC建模搭建自演化系统实验平台.以典型低通切比雪夫滤波器为例,验证了实验平台的有效性.使用SystemC设计自演化系统既可在较高的抽象水平搭建自演化系统模型,加速验证、性能分析和探索系统结构,又可方便地进行软硬件协同设计,并最终达到硬件实现.     

一种基于8 bit CPU核的混合SoC验证平台的设计

提出了一种基于8 bit CPU的混合信号SoC的验证平台.该平台能够完成IP模块验证、软硬件协同验证、混合验证等关键验证流程.该验证平台已经成功地应用在某混合信号SoC的设计上,并在0.35 μm CMOS工艺上进行了实现.该验证平台对其它混合SoC设计具有一定的参考作用.     

基于SoC平台的H.264解码器IP核设计

介绍了SoC的发展概况和趋势,提出了一种基于SoC平台的H．264解码器优化设计架构。在设计中采取了灵活的帧场自适应解码策略,对于总线时序需求较高的模块采用了流水线设计,对总线进行了时分复用;在可变长解码部分．对各个功能模块进行了控制分离,这些优化除了可有效地减小时钟频率需求外,还可在一定程度上兼容其它的视额压缩标准．如MPEG-2。最后实现了这个设计,并给出了实验结果。     

移动核心网应用NFV的关键问题探讨及实践

基于网络功能虚拟化的背景,探讨了移动核心网应用网络功能虚拟化(NFV)需要解决的3大关键技术:基础设施平台选择、核心网云管理架构设计和转发面性能加速,并基于NFV架构定义了一种移动核心网的云管理系统架构。与传统电信核心网管理相比,该系统架构增加了对硬件资源、虚拟资源层、虚拟化网元以及完整网络功能的管理、编排和调度,增加了虚拟网元管理和虚拟网元之间的接口,增强了对通用硬件运行状态的管理能力,以便能更及时、更全面地管理通用硬件和虚拟网元,实现实时的资源和功能调度。     

An algorithm for the selection of effective error correction coding in wireless networks based on a lookup table structure

In this paper, we propose an adaptive Forward Error Correction (FEC) coding algorithm at the Medium Access Control (MAC) layer used in wireless networks. Our algorithm is based on the lookup table architecture, including a distance lookup table and a bit error rate lookup table. These tables will store the best value of the FEC codes based on different distances and bit error rates. Because radio channels change over time, the bit error rate is always changing, or in the case of mobile nodes, when the transmission distance changes, the bit error rate also changes, so previously proposed algorithms take longer to find the optimal value of the FEC code for data transmission. Our proposed algorithm, however, is based on 2 lookup tables, and thus, it can always quickly select an optimal FEC code during early data transmissions and achieve high performance. We compare our algorithm with other methods based on performance metrics such as the recovery overhead of FEC codes, energy efficiency, and peak‐signal‐to‐noise ratio values in the case of image transmission. Our simulation indicates that the proposed algorithm achieves better performances and proves the correctness of the proposed lookup table architecture.     

Dynamic computational blocks for bit-level systolic arrays

Integrated dynamic logic trees with latches provide cost effective circuit techniques for building massively pipelined, systolic, computational blocks operating at the bit level. Recent results have demonstrated that dynamic pipelines are capable of very high switching speeds with appropriate circuit design techniques. In this paper we trade some of this speed for much higher functionality of each logic block. The resulting throughput rate remains sufficiently high for useful applications, but results in substantial area and power savings. Design techniques for the individual logic trees (switching trees) are based on simple graph theoretic rules. Examples are shown to support the technique     

一种流水线型ADC的时序改进技术研究

对一种流水线型模数转换器(ADC)的时序电路进行了改进研究。改进时序延长了余量增益单元MDAC部分加减保持相位的时长,可以在不增加功耗与面积的情况下,将一种10位流水线型ADC在20 MS/s采样率下的有效位(ENOB)从9.3位提高到9.8位,量化精度提高了5%;将该ADC有效位不低于9.3位的最高采样率从21 MS/s提高到29 MS/s,转换速度提高了35%。ADC的采样频率越高,改进时序带来的效果越显著。该项技术特别适用于高速高精度流水线型ADC,也为其他结构ADC的高速高精度设计提供思路。     

Reducing cell loss in banyan based ATM switching fabrics

In this paper, we propose a new technique for reducing cell loss in multi‐banyan‐based ATM switching fabrics. We propose a switch architecture that uses incremental path reservation based on previously established connections. Path reservation is carried out sequentially within each banyan but multiple banyan planes can be concurrently reserved. We use a conflict resolution approach according to which banyans make concurrent reservation offers of conflict‐free paths to head of the line cells waiting in input buffers. A reservation offer from a given banyan is allocated to the cell whose source‐to‐destination path uses the largest number of partially allocated switching elements which are shared with previously reserved paths. Paths are incrementally clustered within each banyan. This approach leaves the largest number of free switching elements for subsequent reservations which has the effect of reducing the potential of future conflicts and improves throughput. We present a pipelined switch architecture based on the above concept of path‐clustering which we call path‐clustering banyan switching fabric (PCBSF). An efficient hardware that implements PCBSF is presented together with its theoretical basis. The performance and robustness of PCBSF are evaluated under simulated uniform traffic and ATM traffic. We also compare the cell loss rate of PCBSF to that of other pipelined banyan switches by varying the switch size, input buffer size, and traffic pattern. Copyright © 2001 John Wiley & Sons, Ltd.     

Optimization of test resources for 3D SoC based on game theory

The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip (SoC) in semiconductor industry. The rapid development of process technology enables the creation of stacked 3-dimensional (3D) SoC by means of through-silicon-via (TSV). Stacked 3D SoC testing consists of two major issues, test architecture optimization and test scheduling. This paper proposed game theory based optimization of test scheduling and test architecture to achieve win-win result as well as individual rationality for each player in a game. Game theory helps to achieve equilibrium between two correlated sides to find an optimal solution. Experimental results on handcrafted 3D SoCs built from ITC’2 benchmarks demonstrate that the proposed approach achieves comparable or better test times at negligible computing time.     

High performance square rooting circuit using hybrid radix-2 adders

A new high performance bit parallel architecture for computing square roots is proposed. The architecture implements a non-restoring algorithm and is structured as a pipelined cellular array. To improve the performance, hybrid radix-2 adders are used. However, the conventional two's complement representation for both the radicand and square root is maintained     

MCBF: a high-performance scheduling algorithm for buffered crossbar switches

The buffered crossbar architecture is becoming very attractive for the design of high performance routers due the unique features it offers. Many distributed scheduling algorithms have been proposed for this architecture. Despite their distributed nature, the existing schemes require quite a bit of hardware and timing complexity. We propose a novel scheduling scheme named the most critical buffer first (MCBF). This scheme is based only on the internal buffer information and requires much less hardware than the existing schemes. Yet, it exhibits good performance and outperforms all its competitors. More interestingly, MCBF shows optimal stability performance while being almost a stateless algorithm.     

Hardware-software partitioning and pipelined scheduling of transformative applications

Transformative applications are computation intensive applications characterized by iterative dataflow behavior. Typical examples are image processing applications like JPEG, MPEG, etc. The performance of embedded hardware-software systems that implement transformative applications can be maximized by obtaining a pipelined design. We present a tool for hardware-software partitioning and pipelined scheduling of transformative applications. The tool uses iterative partitioning and pipelined scheduling to obtain optimal partitions that satisfy the timing and area constraints. The partitioner uses a branch and bound approach with a unique objective function that minimizes the initiation interval of the final design. We present techniques for generation of good initial solution and search-space limitation for the branch and bound algorithm. A candidate partition is evaluated by generating its pipelined schedule. The scheduler uses a novel retiming heuristic that optimizes the initiation interval, number of pipeline stages, and memory requirements of the particular design alternative. We evaluate the performance of the retiming heuristic by comparing it with an existing technique. The effectiveness of the entire tool is demonstrated by a case study of the JPEG image compression algorithm. We also evaluate the run time and design quality of the tool by experimentation with synthetic graphs.     

LotteryBus的设计与实现

为了提高SoC内部总线的性能,优化总线架构.文章提出了一种新颖的LotteryBus总线机制.通过将其与静态优先级及时分复用总线进行比较,介绍了它的特点及其仲裁机制.并且设计和实现了一个4-Masters的LottervBus用于龙芯SoC内部高速总线的改进,功能仿真和FPGA验证证明这一总线机制的可行性和正确性.