An ISDN echo-cancelling transceiver chip set for 2B1Q coded U-interface

A three-chip set for a 2B1Q U-interface transceiver has been developed. The chip set is composed of an analog front-end (AFE), echo-canceller (EC), and receiver (RCV) LSIs. The AFE LSI includes a 12-b accuracy oversampling analog/digital converter. The EC and RCV LSIs are 26- and 16-bit microprogrammable digital signal processors, respectively. A digital phase-locked loop is used to minimize the analog part. Residual echo increase by a timing phase jump is compensated for by a newly introduced additional adaptive filter. Infinite impulse response filters and multiresponse filters reduce the necessary number of taps for both the echo canceller and the decision-feedback equalizer. The AFE and the two digital signal processor LSIs are implemented in 1.6- and 1.2-μm double-metal layer CMOS processes, respectively. A 6-km loop coverage was realized with a less than 10^-7 error rate. Total power consumption by the chip set is 580 mW at 5-V single supply     

A mixed-signal array processor with early vision applications

Many early vision tasks require only 6 to 8 b of precision. For these applications, a special-purpose analog circuit is often a smaller, faster, and lower power solution than a general-purpose digital processor, but the analog chips lack the programmability of digital image processors. This paper presents a programmable mixed-signal array processor which combines the programmability of a digital processor with the small area and low power of an analog circuit. Each processor cell in the array utilizes a digitally programmable analog arithmetic unit with an accuracy of 1.3%. The analog arithmetic unit utilizes a unique circuit that combines a cyclic switched-capacitor analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to perform addition, subtraction, multiplication, and division, Each processor cell, fabricated in a 0.8-μm triple-metal CMOS process, operates at a speed of 0.8 MIPS, consumes 1.8 mW of power at 5 V, and uses 700 μm by 270 μm of silicon area. An array of these processor cells performed an edge detection algorithm and a subpixel resolution algorithm     

Mixed digital/analog signal processing for a single-chip 2B1Q U-interface transceiver

Mixed analog-digital signal processing aspects of a 5-V single-chip U-interface 2B1Q transceiver are discussed. Analog signal processing preconditions the signal by reducing jitter-induced echo and nonlinear echo components, and by maximizing the dynamic range utilization of the 13-b analog-to-digital (A/D) converter. The digital signal processor performs the high-pass filtering, precursor equalization, linear echo cancellation, far-end signal equalization, and timing recovery functions. The analog signal preconditioning technique allows the entire digital signal processing (DSP) section to be designed without a single dedicated multiplier. The U-interface transceiver has been realized in a 1.5-μm double-metal CMOS process, resulting in a circuit area of 77 mm². Total power consumption is 300 mW. To comply with the ANSI-specified performance test procedures, a crosstalk noise generator and injection circuit were custom built along with a jitter generation system, all of which match the ANSI noise and jitter templates. Testing was performed over the 15 ANSI loops and countless other random configurations. Full compliance with the standard protocol and timing limits was achieved on all the loops     

基于FPGA的SDR FM接收机的设计

针对模拟元件制做的传统接收机的相关设备由于工作频率较高导致对元件参数要求高,电路布局布线困难等问题,提出一种利用FPGA芯片作为接收机的重要组成部分,结合简单外围硬件电路共同组成接收机的新方法。通过FPGA的差分I/O引脚完成接收机的模数转换功能,在集成设计环境Vivado中通过调用IP核的方法实现数字下变频和信号解调等功能。实验结果表明,该系统具有成本低、响应快、可靠性高的特点。     

A low-power stereo 16-bit CMOS D/A converter for digital audio

A low-power 16-bit CMOS D/A (digital/analog) converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric averaging technique is used to minimize the harmonic distortion of the converter at high signal levels. The dynamic range is 95 dB. The circuit operates in a time-multiplex mode at a sample frequency of 44 kHz in a power supply range of 2.5-5 V and has a power consumption of 15 mW. A 2-μm CMOS technology is used and the active chip area is 5 mm²      

A digital adaptive beamforming QAM demodulator IC for high bit-ratewireless communications

A very large scale integration (VLSI) implementation of an integrated adaptive beamforming processor and quadrature amplitude modulation (QAM) demodulator which will be incorporated into a frequency-hopped spread spectrum portable receiver for 2.4-GHz industrial, scientific, and medical (ISM) band applications is presented. The chip performs coherent QAM demodulation of variable constellation size and complete adaptive beamforming processing including four-channel adaptive beamforming combining, a fully programmable training processor, a readable/writable system control processor, an acquisition state machine, and a microcontroller interface. Interleaving area intensive blocks such as the 49-tap square-root Nyquist filters and 12×12 b multipliers is employed to reduce chip area. This chip can operate as a stand-alone adaptive beamforming QAM demodulator, or it can work together with an adaptive equalizer for high bit rate indoor wireless applications. The core area of the chip is 6.22 mm×4.58 mm in 0.8-μm CMOS technology, and the power dissipation is 610 mW at 5 V and a 5 MBaud symbol rate. In a 2.2-dB signal-to-interference-and-noise ratio environment, the receiver chip achieves a link quality of 32.6 dB SNR by performing digital adaptive beamforming to null out interferers     

基于开关电容阵列的高速多元激光回波数字化技术

设计了基于新型开关电容阵列技术的激光回波数字化系统,实现了每秒5G个采样点 (Gigabit Samples per Second, GSPS)的采样速率。利用单片模拟数字转换器件(Analog Digital Converter, ADC)实现了多元信号采样。该系统具有很大的发展潜力。介绍了多米诺环形采样器(Domino Ring Sampler, DRS)4的控制策略。设计了基于DRS4芯片的激光回波数字化电路,搭建了激光测试系统,并开展了基于DRS4的信号采样实验。实验结果表明,采用DRS4芯片进行激光回波数字化,能够达到最高5GSPS的采样速率,可实现多元系统设计,增大视场,同时降低系统功耗和成本。     

A Digital Coreless Maximum Power Point Tracking Circuit for Thermoelectric Generators

This paper describes a maximum power point tracking (MPPT) circuit for thermoelectric generators (TEG) without a digital controller unit. The proposed method uses an analog tracking circuit that samples the half point of the open-circuit voltage without a digital signal processor (DSP) or microcontroller unit for calculating the peak power point using iterative methods. The simulation results revealed that the MPPT circuit, which employs a boost-cascaded-with-buck converter, handled rapid variation of temperature and abrupt changes of load current; this method enables stable operation with high power transfer efficiency. The proposed MPPT technique is a useful analog MPPT solution for thermoelectric generators.     

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.     

A CMOS triple 100-Mbit/s video D/A converter with shift register and color map

A 100-Mb/s CMOS video digital-to-analog converter (VDAC) chip is described. The VDAC provides all output functions for a four-plane color video subsystem. Included in this chip are: direct drivers for 75-/spl Omega/ cables; three 100-MHz 4-bit DACs; a color-map memory; video shift registers; cursor logic and a processor interference. The design approaches for both the analog and digital circuitry are discussed. The bench and automatic testing of this high-speed, high-pin-count, combined analog/digital chip are presented.     

A 540-MHz 10-b polar-to-Cartesian converter

A 10-b polar-to-Cartesian converter for generating digital sine and cosine waveforms simultaneously with a maximum sample rate of 540 MHz is presented. The converter is derived from a coordinate rotation digital computer (CORDIC) processor. Implementation details and the chip layout are given. The converter is implemented in a 1-μm 13-GHz triple-level interconnect bipolar process, requiring 1000 mW from a single 5-V supply. The die size is 25 mm²     

A 3-V 0.5-μm CMOS A/D audio processor for a microphone array

A 0.5-μm 3-V CMOS mixed-mode audio processor is presented. It is mainly composed of 11 low-noise input channels and a dedicated digital audio processor. Analog input signals are provided through an 11-microphone array. The chip size is about 50 mm², and the power dissipation is less than 100 mW. This circuit is dedicated to multimedia applications     

基于锂电池化成的新型双向DC／DC拓扑结构研究与建模

提出一种用于锂电池化成技术的新型双向DC／DC拓扑结构。采用两级双向DC／DC拓扑结构,一级使用半桥双向变换器,另一级使用Buck—boost双向变换器,用数字信号处理器对Buck—boost双向变换器进行闭环控制,能实现输入电压和输出电压有较大压差的情况下进行变换。在Matlab／Simlink下对该拓扑结构进行验证。结果表明,该变换器性能稳定,能有效地实现3V电池电压和400V母线电压双向变换。     

一种单芯片DVB-C解调器的VLSI实现

设计了一个单芯片实现的用于DVB-C的QAM解调器.片上集成有3.3V 10位精度的40MSPS模数转换器及FEC前向纠错解码器.该芯片支持4～256QAM多种模式,最高码率达80Mbps,具有宽的载波频偏捕获范围.采用改进的算法及VLSI实现结构,性能稳定,面积优化.采用SMIC 0.25μm 1P5M混合信号CMOS工艺制造,面积为3.5mm×3.5mm,最大功耗为447mW.     

宽带超短波射频前端的设计和实现

宽带超短波射频前端是软件无线电通信平台的关键部分之一。在此介绍了集成宽带调制芯片TRF372017和解调芯片ADRF6850,设计了宽带超短波射频模块的实现方案。基于这两款芯片分别实现了发送电路和接收电路,并结合软件无线电基带处理平台加载了宽带通信波形进行测试。测试结果显示,该射频模块具有较好的性能,且具有体积小,功耗低,增益控制范围大等优点。     

A DSP-based active disturbance rejection control design for a 1-kW H-bridge DC-DC power converter

This paper presents the design and implementation of an advanced digital controller for a 1-kW H-bridge dc-dc power converter. A new control algorithm based on the active disturbance rejection concept is developed to cope with the highly nonlinear dynamics of the converter and the disturbances. An experimental digital control system is used to implement the new control strategy. It consists of a digital control board based on the TMS320C6711 digital signal processor chip, an analogy I/O board, and a complex programmable logic device pulsewidth-modulation generation board. Using a newly developed bandwidth-parametrization technique, an autotuning method based on noise quantification is also developed and tested. Experimental results show the advantages and flexibilities of the new control method for the H-bridge dc-dc power converter.     

A combined low power SAR capacitance-to-digital analog-to-digital converter for multisensory system

A combined successive approximation (SAR) capacitance-to-digital converter (CDC)/analog-to-digital converter (ADC) for biomedical multisensory system is presented in this paper. The two converters have same circuit blocks and can be exchanged by four switches. Capacitance or voltage from different sensing elements can be measured and converted to digital output directly. This single chip takes place of separated CDC and ADC so that the power consumption of the multisensory system is reduced. The asynchronous SAR circuit has low power and small area. A dynamic comparator with zero-static power is adopted. Switches are carefully designed to reduce the non-idealities of the converter. Several techniques, such as bootstrapped switches, bottom-plate sampling, dummy switches are used to improve the performance of the circuit. The CDC/ADC is fabricated in 0.18 μm CMOS process. Measurement results show that the ENOB of this 11 bits converter is 10.15 bits and its FOM is 45 fJ/conversion-step under 200 kHz sampling. The power consumption is 9.4 μW with 1.4 V power supply voltage and the core area is 0.1764 mm².     

基于Credence Gemini500的内嵌式AD转换器测试方法研究

本文中应用Credence公司的Gemini500测试系统对某一SoC芯片内嵌模数转换器进行了测试。根据芯片功能分析和封装形式,对测试板进行了优化设计。根据内嵌式ADC的时序特点进行了测试向量的设计。     

基于TMS320VC5409的水声通信Modem设计与实现

介绍水声通信Modem系统的组成结构和软硬件总体设计方案。系统包括以DSP芯片TMS320VC5409为核心的数字信号处理电路、USB接口电路、前置模拟终端（AFE）电路和换能器。通过该方法可以实现水声通信Modem系统的远距离数据传输,迅速实现DSP与计算机之间的数据交换。     

A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offsetcancellation limiting amplifier

This paper presents a low-voltage low-power IF 455-kHz signal processor that contains a three-stage limiting amplifier and an FM/FSK demodulator. The limiting amplifier uses an on-chip feedforward offset cancellation circuit. The FM/FSK demodulator employs a quadrature detector that is composed of an on-chip phase detector and an external tank phase shifter. The demodulation constant is 20 mV/kHz with masimum ±10-kHz frequency deviation. The IF signal processor that consumes 2.3 mW from a single 2-V power supply demonstrates a high sensitivity of -72 dBm. It occupies an active area of 0.2 mm² using 0.6-μm digital CMOS technology