High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

Low Turn-On Voltage and High-Current $hbox{InP}/ hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Double Heterojunction Bipolar Transistors

We report on the dc and microwave characteristics of an $ hbox{InP/In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ double heterojunction bipolar transistor grown by solid-source molecular beam epitaxy. The pseudomorphic $hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}$ base reduces the conduction band offset $Delta E_{C}$ at the emitter/base junction and the base band gap, which leads to a very low $V_{rm BE}$ turn-on voltage of 0.35 V at 1 $hbox{A/cm}^{2}$ . A current gain of 125 and a peak $f_{T}$ of 238 GHz have been obtained on the devices with an emitter size of $hbox{1}times hbox{10} muhbox{m}^{2}$, suggesting that a high collector average velocity and a high current capability are achieved due to the type-II lineup at the InGaAsSb/InGaAs base/collector junction.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

Lattice-Mismatched $hbox{In}_{0.4}hbox{Ga}_{0.6} hbox{As}$ Source/Drain Stressors With In Situ Doping for Strained $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel n-MOSFETs

We report the first demonstration of a strained $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ channel n-MOSFET featuring in situ doped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ source/drain (S/D) regions. The in situ silicondoped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ S/D was formed by a recess etch and a selective epitaxy of $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ in the S/D by metal–organic chemical vapor deposition. A lattice mismatch of $sim$0.9% between $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ and $hbox{In}_{0.4} hbox{Ga}_{0.6}hbox{As}$ S/D gives rise to lateral tensile strain and vertical compressive strain in the $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ channel region. In addition, the in situ Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

Electrical Properties of Amorphous $hbox{Bi}_{5} hbox{Nb}_{3}hbox{O}_{15}$ Thin Film for RF MIM Capacitors

Amorphous $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}(hbox{B}_{5} hbox{N}_{3})$ film grown at 300 $^{circ}hbox{C}$ showed a high-$k$ value of 71 at 100 kHz, and similar $k$ value was observed at 0.5–5.0 GHz. The 80-nm-thick film exhibited a high capacitance density of 7.8 fF/$muhbox{m}^{2}$ and a low dissipation factor of 0.95% at 100 kHz with a low leakage-current density of 1.23 nA/ $hbox{cm}^{2}$ at 1 V. The quadratic and linear voltage coefficient of capacitances of the $hbox{B}_{5}hbox{N}_{3}$ film were 438 ppm/$hbox{V}^{2}$ and 456 ppm/V, respectively, with a low temperature coefficient of capacitance of 309 ppm/$^{circ}hbox{C}$ at 100 kHz. These results confirmed the potential of the amorphous $hbox{B}_{5}hbox{N}_{3}$ film as a good candidate material for a high-performance metal–insulator–metal capacitors.      

Electrical Properties of $hbox{Ga}_{2}hbox{O}_{3}/ hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of $hbox{Ga}_{2}hbox{O}_{3}/hbox{GaAs}$ interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm ($hbox{0.9} leq hbox{EOT} leq hbox{3.9} hbox{nm}$) have been characterized by capacitance–voltage measurements. Midgap interface state density $D_{rm it}$, effective workfunction $phi_{m}$, fixed charge $Q_{f}$, dielectric constant $kappa$, and low field leakage current density are $hbox{2} times hbox{10}^{11} hbox{cm}^{-2} cdot hbox{eV}^{-1}$, 4.93 eV, $-hbox{8.9} times hbox{10}^{11} hbox{cm}^{-2}$, 19.5, and $hbox{10}^{-9}{-} hbox{10}^{-8} hbox{A/cm}^{2}$, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.      

High-Density and Low-Leakage-Current MIM Capacitor Using Stacked $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Insulators

We have fabricated high-$kappa hbox{Ni}/hbox{TiO}_{2}/hbox{ZrO}_{2}/ hbox{TiN}$ metal–insulator–metal (MIM) capacitors. A low leakage current of $hbox{8} times hbox{10}^{-8} hbox{A/cm}^{2}$ at 125 $^{circ}hbox{C}$ was obtained with a high 38- $hbox{fF}/muhbox{m}^{2}$ capacitance density and better than the $hbox{ZrO}_{2}$ MIM capacitors. The excellent device performance is due to the lower electric field in 9.5-nm-thick $hbox{TiO}_{2}/ hbox{ZrO}_{2}$ devices to decrease the leakage current and to a higher $kappa$ value of 58 for $ hbox{TiO}_{2}$ as compared with that of $hbox{ZrO}_{2}$ to preserve the high capacitance density.      

Effective Modulation of Quadratic Voltage Coefficient of Capacitance in MIM Capacitors Using $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ Dielectric Stack

We report the first demonstration of metal–insulator–metal (MIM) capacitors with $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ stacked dielectrics for precision analog circuit applications. By using the “canceling effect” of the positive quadratic voltage coefficient of capacitance (VCC) of $hbox{Sm}_{2}hbox{O}_{3}$ and the negative quadratic VCC of $hbox{SiO}_{2}$, MIM capacitors with capacitance density exceeding 7.3 $hbox{fF}/muhbox{m}^{2}$ , quadratic VCC of around $-hbox{50} hbox{ppm/V}^{2}$ , and leakage current density of $hbox{1} times hbox{10}^{-7} hbox{A/cm}^{2}$ at $+$3.3 V are successfully demonstrated. The obtained capacitance density and quadratic VCC satisfy the technical requirements specified in the International Technology Roadmap for Semiconductors through the year 2013 for MIM capacitors to be used in precision analog circuit applications.      

0.8-V Supply Voltage Deep-Submicrometer Inversion-Mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFET

We report the experimental demonstration of deep-submicrometer inversion-mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFETs with ALD high- $k$ $hbox{Al}_{2}hbox{O}_{3}$ as gate dielectric. In this letter, n-channel MOSFETs with 100–200-nm-long gates have been fabricated. At a supply voltage of 0.8 V, the fabricated devices with 200–130-nm-long gates exhibit drain currents of 232–440 $muhbox{A}/muhbox{m}$ and transconductances of 538–705 $muhbox{S}/muhbox{m}$. The 100-nm device has a drain current of 801 $muhbox{A}/muhbox{m}$ and a transconductance of 940 $muhbox{S}/muhbox{m}$. However, the device cannot be pinched off due to severe short-channel effect. Important scaling metrics, such as on/off current ratio, subthreshold swing, and drain-induced barrier lowering, are presented, and their relations to the short-channel effect are discussed.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

A Theoretical Comparison of the Breakdown Behavior of $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ and InP Near-Infrared Single-Photon Avalanche Photodiodes

We study the breakdown characteristics and timing statistics of InP and $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ single-photon avalanche photodiodes (SPADs) with avalanche widths ranging from 0.2 to 1.0 $mu{hbox {m}}$ at room temperature using a random ionization path-length model. Our results show that, for a given avalanche width, the breakdown probability of $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ SPADs increases faster with overbias than InP SPADs. When we compared their timing statistics, we observed that, for a given breakdown probability, InP requires a shorter time to reach breakdown and exhibits a smaller timing jitter than $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ . However, due to the lower dark count probability and faster rise in breakdown probability with overbias, $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ SPADs with $hbox{avalanche} hbox{widths}leq 0.5 mu{hbox {m}}$ are more suitable for single-photon detection at telecommunication wavelengths than InP SPADs. Moreover, we predict that, in InP SPADs with $hbox{avalanche} hbox{widths}leq 0.3 mu{hbox {m}}$ and $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ SPADs with $hbox{avalanche} hbox{widths}leq 0.2 mu{hbox {m}}$, the dark count probability is higher than the photon count probability for all applied biases.      

Improved Stress Reliability of Analog Metal–Insulator–Metal Capacitors Using $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Dielectrics

We have studied the stress reliability of high-$kappa$ $hbox{Ni/TiO}_{2}/hbox{ZrO}_{2}/hbox{TiN}$ metal–insulator–metal capacitors under constant-voltage stress. The increasing $hbox{TiO}_{2}$ thickness on $hbox{ZrO}_{2}$ improves the 125-$^{circ}hbox{C}$ leakage current, capacitance variation $(Delta C/C)$, and long-term reliability. For a high density of 26 $hbox{fF}/mu hbox{m}^{2}$ , good extrapolated ten-year reliability of small $Delta C/ break C sim hbox{0.71}%$ is obtained for the $ hbox{Ni/10-nm-}hbox{TiO}_{2}/hbox{6.5-nm-} hbox{ZrO}_{2}/break hbox{TiN}$ device at 2.5-V operation.      

Fabrication and Properties of $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85} hbox{Ti}_{3}hbox{O}_{12}/breakhbox{HfO}_{2}/hbox{Si}$ Structure for Ferroelectric DRAM (FEDRAM) FET

Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors with 400-nm-thick $hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}$ (BNdT) ferroelectric film and 4-nm-thick hafnium oxide $(hbox{HfO}_{2})$ layer on silicon substrate have been fabricated and characterized. It is demonstrated that the $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}/ hbox{HfO}_{2}/hbox{Si}$ structure exhibits a large memory window of around 1.12 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 10% degradation in the memory window after $hbox{10}^{10}$ switching cycles. The retention time is 100 s, which is enough for ferroelectric DRAM field-effect-transistor application. The excellent performance is attributed to the formation of well-crystallized BNdT perovskite thin film on top of the $ hbox{HfO}_{2}$ buffer layer, which serves as a good seed layer for BNdT crystallization, making the proposed $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}/ hbox{HfO}_{2}/hbox{Si}$ suitable for high-performance ferroelectric memories.      

Strain Enhanced nMOS Using In Situ Doped Embedded $hbox{Si}_{1 - x}hbox{C}_{x}$ S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process

This letter reports on the implementation of high carbon content and high phosphorous content $hbox{Si}_{1 - x}hbox{C}_{x}$ layers in the source and drain regions of n-type MOSFET in a 65-nm-node integration scheme. The layers were grown using a novel epitaxial process. It is shown that by implementing stressors with $x approx hbox{0.01}$ , nMOSFET device performance is enhanced by up to 10%, driving 880 $mu hbox{A}/muhbox{m}$ at 1-V $V_{rm DD}$. It is also demonstrated that the successful implementation of $hbox{Si}_{1 - x} hbox{C}_{x}$ relies on the careful choice of integration and epitaxial layer parameters. There is a clear impact of the postepitaxial implantation and thermal treatment on the retained substitutional C content $([C_{rm sub}])$. Furthermore, adding a Si capping layer on top of the $hbox{Si}_{1 - x}hbox{C}_{x}$, greatly improves upon the stressors' stability during the downstream processing and the silicide sheet resistance.      

Nonvolatile-Memory Characteristics of $hbox{AlO}^{-}$ -Implanted $hbox{Al}_{2}hbox{O}_{3}$

The nonvolatile-memory (NVM) characteristics of $hbox{AlO}^{-}$ -implanted $hbox{Al}_{2}hbox{O}_{3}$ structures are reported and shown to exhibit promising behaviors, including fast program/erase speeds and high-temperature data retention. Photoconductivity spectra show the existence of two dominant trap levels, located at around 2 and 4 eV below the conduction band minimum of $hbox{Al}_{2}hbox{O}_{3}$, and our calculations show that these levels are likely attributed to the defects in the $hbox{Al}_{2}hbox{O}_{3}$, such as the Al–O divacancy. The relative concentrations of these defects vary with the implant fluence and are shown to explain the NVM characteristics of the samples irradiated to different fluences.      

Pentacene-Based Low-Voltage Strain Sensors With PVP/$ hbox{Ta}_{2}hbox{O}_{5}$ Hybrid Gate Dielectrics

Field-controllable pentacene-semiconductor-based strain sensors were fabricated with hybrid gate dielectrics using polyvinyl phenol (PVP) and high-$k$ inorganic tantalum pentoxide $(hbox{Ta}_{2}hbox{O}_{5})$ onto polyethylene naphthalate films. The $hbox{Ta}_{2}hbox{O}_{5}$ gate-dielectric layer combined with a thin PVP layer to form very smooth and hydrophobic surfaces turns out to improve the molecular structures of pentacene films significantly. The PVP– $hbox{Ta}_{2}hbox{O}_{5}$ hybrid-gate-dielectric films exhibit a high dielectric constant of 19.27 and a leakage-current density of as low as 100 $hbox{nA/cm}^{2}$ . The sensors employing a thin-film-transistor-like Wheatstone bridge configuration able to operate at reduced voltage ($sim$4 V) show good device characteristics with a field-effect mobility of 1.89 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and a threshold voltage of $-$0.5 V. The strain sensor characterized with bending at 45$^{circ}$ with respect to the bridge bias direction with different bending radii of 50-, 40-, 30-, 20-, and 8-mm displays output signals improved in linearity in a low range of operating voltages.