Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

Composite TiSi/sub 2//n+ Poly-Si Low-Resistivity Gate Electrode and Interconnect for VLSI Device Technology

A composite polycide structure consisting of refractory metal silicide film on top of polysilicon has been considered as a replacement for polysilicon as a gate electrode and interconnect line in MOSFET integrated circuits. This paper presents fine-line patterning techniques and device characteristics of MOSFET's with a TiSi/sub 2/ polycide gate. A coevaporated TiSi/sub 2/ polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi/sub 2/ because of lower oxygen contamination. The coevaporation technique to form TiSi/sub 2/ polycide with a sheet resistivity of 1 Omega/square (bulk resistivity of 21 µOmega · cm) is described. Anisotropic etching of nominally 1-/spl mu/m lines with a 15 : 1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates. In addition, the specific contact resistivity between Al and TiSi/sub 2/ polycide is lower than the contact resistivity between Al and polysilicon by one order of magnitude.     

Composite TiSi2/n + poly-Si low-resistivity gate electrode and interconnect for VLSI device technology

A composite polycide structure consisting of refractory metal silicide film on top of polysilicon has been considered as a replacement for polysilicon as a gate electrode and interconnect line in MOSFET integrated circuits. This paper presents fine-line patterning techniques and device characteristics of MOSFET's with a TiSi2polycide gate. A coevaporated TiSi2polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi2because of lower oxygen contamination. The coevaporation technique to form TiSi2polycide with a sheet resistivity of 1 Ω/square (bulk resistivity of 21 µΩ.cm) is described. Anisotropic etching of nominally 1-µm lines with a 15:1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates. In addition, the specific contact resistivity between Al and TiSi2polycide is lower than the contact resistivity between Al and polysilicon by one order of magnitude.     

Conductivity changes in tungsten silicide films due to rapid thermal processing

Several limitations of the polysilicon gate in VLSI have led to the development of a silicide/polysilicon material as all alternative to polysilicon. Recently, rapid thermal processing has been investigated for annealing such polycide films. We report here the electrical-conductivity changes during the process of rapid thermal annealing in CVD tungsten silicide films. It is shown that electrical resistivity initially increases due to changes in the silicon to tungsten ratio and then drops to about one-tenth of the initial value, thus suggesting a minimum time and power required for achieving low-resistivity tungsten silicide films in VLSI interconnections.     

Composite silicide gate electrodes—Interconnections for VLSI device technologies

A potentially severe limit on density, performance, and wirability of polysilicon-gate technologies for VLSI applications, is the high resistivity of polycrystalline silicon. Composite structures of highly conductive molybdenum or tungsten disilicide on top of polysilicon (polycide) are shown to be a viable alternative gate electrode and interconnect level. Sheet resistance values of 1-3 Ω/□ for an integrated structure are easily attainable. IGFET devices fabricated to channel lengths of ≥ 1.4 µm show the polycide devices to be indistinguishable from normal polysilicon gate devices.     

Composite Silicide Gate Electrodes -- Interconnections for VLSI Device Technologies

A potentially severe limit on density, performance, and virability of polysilicon-gate technologies for VLSI applications, is the high resistivity of polycrystalline silicon. Composite structures of highly conductive molybdenum or tungsten disilicide on top of polysilicon (polycide) are shown to be a viable alternative gate electrode and interconnect level. Sheet resistance values of 1-3 Omega//spl square/ for an integrated structure are easily attainable. IGFET devices fabricated to channel lengths of >=1.4 /spl mu/m show the polycide devices to be indistinguishable from normal polysilicon gate devices.     

Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects

A study of the refractory-gate metallization schemes had been undertaken to provide a low-resistivity metallization for LSI and VLSI. In this paper, we describe an overview of the efforts made in this direction and present two different metallization schemes which lead to a resistivity of <=20 and 40 /spl mu//spl Omega/spl dot/cm at the gate level. These schemes involve formation of titanium and tantalum silicides on polysilicon gates, respectively. The recommended structure ia a metal or a cosputtered alloy/polysilicon/gate oxide/substrate which, when sintered, gives the desired structure silicide/polysilicon/gate oxide substrate. By the use of 1000-/spl aring/ Ti or Ta, the sheet resistance of nearly 1 or 2 Omega//spl square/, respectively, can be routinely obtained. The silicides are mechanically strong and can be dry etched using radial-flow or barrel-type plasma reactors. The Ta silicide structure is found to be very stable throughout standard processing and can be retrofitted in the present processing sequence. Ti silicide structures are similarly stable except for the reactivity of the silicide with HF-containing reagents. The Ti silicide metallization scheme can therefore be employed in processing with changes incorporated to avoid HF-silicide contact.     

Refractory silicides of titanium and tantalum for low-resistivity gates and interconnects

A study of the refractory-gate metallization schemes had been undertaken to provide a low-resistivity metallization for LSI and VLSI. In this paper, we describe an overview of the efforts made in this direction and present two different metallization schemes which lead to a resistivity of ≤20 and 40 µΩ.cm at the gate level. These schemes involve formation of titanium and tantalum silicides on polysilicon gates, respectively. The recommended structure is a metal or a cosputtered alloy/polysilicon/gate oxide/substrate which, when sintered, gives the desired structure silicide/polysilicon/gate oxide substrate. By the use of 1000-Å Ti or Ta, the sheet resistance of nearly 1 or 2 Ω/□, respectively, can be routinely obtained. The silicides are mechanically strong and can be dry etched using radial-flow or barrel-type plasma reactors. The Ta silicide structure is found to be very stable throughout standard processing and can be retrofitted in the present processing sequence. Ti silicide structures are similarly stable except for the reactivity of the silicide with HF-containing reagents. The Ti silicide metallization scheme can therefore be employed in processing with changes incorporated to avoid HF-silicide contact.     

Submicrometer-channel CMOS for low-temperature operation

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n⁺-poly gate for n-channel and p⁺-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.     

Titanium nitride local interconnect technology for VLSI

This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n⁺and p⁺junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n⁺and p⁺junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils²feasible with 1-µm design rules, is also discussed.     

Formation of TiSi2 and shallow junction byAs+ ion-beam mixing and infrared rapid heat treatment

A technique for forming shallow junctions with low-resistance silicide contacts developed for the use in VLSI with scaled MOSFETs is discussed. The salicide (self-aligned silicide) MOSFET gate and source-drain features self-aligned refractory metal silicide and are isolated from one another even without any insulating spacer on the gate sides. A critical step in such a MOSFET fabrication process is the ion implantation through metal silicidation technique, which includes As⁺ ion-beam-induced titanium-silicon interface mixing and infrared rapid heat treatment to form simultaneously the n⁺-p junction and a high-quality TiN covered TiSi₂ contact layer     

亚微米CMOS IC中自对准硅化物工艺的研究

自对准硅化钛工艺有许多重要的优点.但也存在栅氧化物的完整性、硅化物桥接短路、pn结损伤、二极管特性退化等问题.文章针对这些问题,在硅化前和硅化后的清洗、硅化的快速退火处理、接触电阻最佳化以及在硅化物上的接触孔腐蚀的选择性等方面进行了改进,有效地解决了问题.     

Work function measurement of tungsten polycide gate structures

Three MOS gate structures; polysilicon, tungsten silicide and tungsten polycide, were fabricated and their workfunctions measured with the high frequency C-V technique. The work functions were 4.14 ev and 4.82 ev for phosphorus doped polysilicon and silicon-rich tungsten silicide, respectively. The tungsten polycide structure, however, showed a variance between 4.14 ev and 4.38 ev for different experiments. The polycide MOS device threshold was about 0.15 volt higher than that of polysilicon. Phosphorus out-diffusion and tungsten diffusion along polysilicon grain boundaries were postulated to explain this phenomenon.     

A polycide gate electrode with a conductive diffusion barrierformed with ECR nitrogen plasma for dual gate CMOS

A simple diffusion barrier technology for polycide gate electrodes is presented. An extremely thin silicon nitride layer is formed by poly Si surface nitridation with ECR nitrogen plasma of only nitrogen gas and without substrate heating. The silicon nitride layer acts as an excellent barrier to impurity diffusion from polysilicon to silicide. It was found that barrier formation with ECR nitrogen plasma results in no fatal degradation in the MOS interface characteristics. This technology is very effective for making dual polycide gates inexpensively due to its simplicity and a good affinity with conventional ULSI fabrication processes     

Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

An As-P double-diffused lightly doped drain (LDD) device has been designed and fabricated with a self-aligned titanium disilicide process. The device design was aided by using an analytical one-dimensional model, and analytic results agree well with experimental data on the avalanche breakdown voltage gain and the ratio of substrate current to source current. Threshold voltage and subthreshold characteristics of this device do not deviate from those of a conventional device without LDD and silicide. The drain avalanche breakdown voltage of the LDD device is higher by 2.5 V over the conventional device. Transconductance degradation was observed for the LDD devices due to the inherently high source-drain series resistance of the LDD structure. Substrate current is reduced and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain diffusion and the polysilicon gate to 3 Ω/sq compared with 150 Ω/sq of the unsilicided counterparts. It is also found that larger polysilicon grain size increases the sheet resistance of the silicide gate due to discontinuous titanium disilicide formation on top of polysilicon.     

Transistor off-state leakage current induced by TiSi2pre-amorphizing implant in a 0.20 μm CMOS process

We report on an anomalous off-state leakage current found in NMOS devices fabricated with a pre-amorphizing (PA) implant before titanium silicide formation. We present data which indicates that the leakage current is caused by channeling of the arsenic PA implant through the polysilicon gate. An angled PA implant is shown to prevent the channeling and allow the fabrication of well-behaved devices with low resistance titanium silicide     

Quadruply self-aligned MOS (QSA MOS)—A new short-channel high-speed high-density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually self-aligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for high conductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F × 2F cell (6 µm²/cell, namely 3 × 2 mm²/1 Mbit in 1-µm rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

1 µm MOSFET VLSI technology: Part VII—Metal silicide interconnection technology—A future perspective

A major limitation of polycrystalline silicon as a gate material for VLSI applications is its limited conductivity which restricts its usefulness as an interconnection level. An alternative approach which combines a doped polycrystalline silicon layer with a high-conductivity metal silicide such as WSi2(polycide) is described. Such polycide layers are demonstrated to provide at least an order of magnitude improvement in interconnection resistance relative to polycrystalline silicon while maintaining the reliability of the polycrystalline silicon gate and the ability to form passivating oxide layers under typical polycrystalline silicon processing conditions.     

Technology limitations for N+/P+ polycidegate CMOS due to lateral dopant diffusion in silicide/polysilicon layers

The device degradation of dual-polycide-gate N⁺/P⁺ CMOS polycide transistors due to the lateral diffusion of dopants in the silicides is studied using a coupled 2-D process and device simulator. Design rule spacings between the NMOS and the PMOS transistor are given for various NMOS:PMOS gate area ratios and thermal processing conditions. The simulations show that contrary to previous findings, micrometer and submicrometer spacings are possible for certain silicide technologies using low-temperature or short higher-temperature furnace steps. Simulations show that CoSi₂ and TiSi₂ appear to be better candidates for submicrometer dual-gate applications than WSi₂     

Reduced oxide charge trapping and improved hot-electron reliabilityin submicrometer MOS devices fabricated by titanium salicideprocess

The effects of the titanium salicide (self-aligned silicide) process on the reliability of very-thin-gate-oxide MOSFETs have been studied. It is shown that the titanium salicide process, as compared to the conventional poly-Si gate process, has reduced electron and hole trapping in the oxide and improved hot-electron reliability. It is shown that these phenomena are related to the reduced hydrogen content in the oxide as revealed by a secondary ion mass spectrometry (SIMS) analysis