The dV/dt capability of MOS-gated thyristors

In this paper, a detailed study of the dV/dt capability of MOS-gated thyristors is performed. It is shown that in addition to the conventional mode of dV/dt-induced turn-on in thyristors, termed the intrinsic mode, there exists another distinct mode of dV/dt-induced turn-on, peculiar to the MOS-gated thyristor structure, which the authors term the extrinsic dV/dt mode. The effective dV/dt capability is determined by both modes and is degraded by the presence of an external gate-cathode resistance and parasitic gate-anode capacitance. The existence of these two modes of dV/dt-induced turn-on is demonstrated experimentally, and the effect of device parameters on the dV/dt capability is studied     

The dV / dt capability of field-controlled thyristors

A detailed analysis of thedV/dtcapability of field-controlled thyristors is presented. It is demonstrated for the first time thatdV/dtinduced turn-on can occur in these devices due to gate debiasing as a result of capacitive gate current flow if a large series gate resistance is present in the circuit. A theoretical analysis of thedV/dtcapability is presented based upon this mechanism which predicts that thedV/dtcapability will decrease inversely with increasing gate series resistance at low values and become independent of the gate series resistance at very high values. The quantitative calculations of thedV/dtcapability that have been made by using this theory are in very good agreement with measurements taken on asymmetrical field-controlled thyristors fabricated from wafers of various thickness. The results obtained in this study allow the conclusion that thedV/dtcapability of field-controlled thyristors are superior to that of conventional thyristors.     

The dV/dt capability of double-interdigitated (TIL) thyristors

This work presents an alternative solution, with respect to the conventional cathode-emitter shorts or MOS-controlled emitter shorts, for achieving virtual immunity to the parasitic action of displacement currents in power thyristors. The developed simple design/ technological procedure, based upon the novel double-interdigitated or two interdigitation level (TIL) gate-cathode configuration with a coarse geometry, offers a fair balance between technological simplicity/cost effectiveness and overall device performance. Based upon the developed design guidelines, two sets of gold-doped thyristors with different geometrical configurations and current-voltage handling capabilities were produced. The performed measurements have shown that both sets of TIL thyristors possess an extremely high value of the maximum permissible critical rate of rise of the off-state voltage (dV/ dt capability) even under open-gate conditions. When the gate is connected to the cathode, the TIL thyristors are practically immune to the action of displacement currents. Unlike thyristors using conventional emitter shorts, the TIL-type devices possess a good static and dynamic turn-on/latching sensitivity and have low on-state losses at high-current densities.     

An acoustic technique for studying thyristor turn-on action and di/dt capability

Mechanical shock waves have been detected emanating from the initial turn-on region in thyristors. This phenomenon has enabled the position of the ignition point to be determined and has allowed nondestructive examination of the effect of some parameters on di/dt capability.     

The di/dt capability of field-controlled thyristors

Limitations to the di/dt capability of field controlled thyristors are discussed. Although the di/dt rating of these devices is not limited by plasma spreading as in conventional thyristors, destructive di/dt induced failure in surface gate devices has been observed. This failure has been shown to be due to non uniform turn-on in these devices due to inhomogeneities in the base region resistivity. Based upon this failure mechanism, it can be concluded that devices with higher di/dt ratings can be fabricated by decreasing the cathode and gate finger lengths and using thicker cathode metallization. In addition an improved device structure with vertical current flow is described with which further increases in di/dt ratings of these devices can be expected.     

di/dt Noise in CMOS Integrated Circuits

This is an overview paper presenting di/dtnoise from a designers perspective. Analysis and circuit designtechniques are presented taking package parasitics into account.The main focus is on digital CMOS design, but analysis and designsuggestions can easily be extended to mixed-mode design.     

Gate turn-off capability of depletion-mode thyristors

Experimental results are described which demonstrate the ability to switch a thyristor from its ON state to its OFF state by using a depletion layer formed by the application of gate bias to a trench-gate MOSFET integrated within the thyristor structure. The maximum controllable current is found to be a function of the gate bias voltage, the trench depth, and the ambient temperature. The maximum controllable current can be increased by increasing the trench depth and decreasing the p-base sheet resistance. The maximum controllable current decreases at high temperatures, as in the case of other MOS-bipolar devices, but is significantly better than for previous devices. The absolute values of the maximum turnoff current are well above 1000 A/cm² at room temperature and 500 A/cm² at 200°C     

高速大功率半导体开关RSD的di/dt耐量极限值

文章由等离子体双极漂移方程和临界预充电荷条件出发,得出高速大功率半导体开关RSD的di/dt耐量表达式。从外电路和器件结构本身两方面分析了RSD的di/dt耐量的影响因素,并提出了改善di/dt耐量的措施,测试结果证明了理论分析的正确性。     

Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors

As the characteristics of insulated gate transistors [like metal-oxide-semiconductor field-effect transistors and insulated gate bipolar transistors (IGBTs)] have been constantly improving, their utilization in power converters operating at higher and higher frequencies has become more common. However, this, in turn, leads to fast current and voltage transitions that generate large amounts of electromagnetic interferences over wide frequency ranges. In this paper, a new active gate voltage control (AGVC) method is presented. It allows us to control the values of di/dt at turn-on and dv/dt at turn-off for insulated gate power transistors, by acting directly on the input gate voltage shape. In an elementary switching cell, it enables us to strongly reduce over-current generated by the reverse recovery of the free-wheeling diode at turn-on, and oscillations of the output voltage across the transistor at turn-off. In the following sections, the AGVC in open and closed-loop for IGBT is presented, and its performance is compared with that of a more conventional method, i.e., increasing the gate resistance. Robustness of the AGVC is estimated under variations of dc-voltage supply and transistor switched current.     

Predicting the surge capability of power thyristors

A simple and efficient computer-aided method developed for correct prediction of maximum surge capability of power thyristors under single and repetitive 50 Hz halfsine waves of overload current is presented in detail. The validity of the developed method was confirmed by experimental results.     

金属氧化物半导体控制晶闸管的di/dt优化

金属氧化物半导体控制晶闸管(MCT)相比于绝缘栅双极型晶体管(IGBT)具有高电流密度、低导通压降和快速开启等优势,在高压脉冲功率领域具有广阔的应用前景.作为脉冲功率开关,MCT开启过程对输出脉冲信号质量有很大影响.采用理论分析并结合仿真优化重点研究了MCT开启瞬态特性.通过对MCT开启过程进行详细地理论分析推导,给出了MCT开启过程中阳极电流和上升时间的表达式.结合Sentaurus TCAD仿真优化,将MCT开启过程中电流上升速率(di/dt)由40 kA/s提升至80 kA/s,极大地改善了器件开启瞬态特性.最后,总结提出了提高器件开启瞬间di/dt的设计途径.     

提高晶闸管器件对di/dt的耐受能力的途径

介绍了晶闸管器件的通态电流上升率di/dt参数及其损坏晶闸管器件的机理，并进一步介绍了提高晶闸管器件的通态di/dt耐量的设计和工艺方法，及应用过程中限制晶闸管阳极电路的电流上升率，保护晶闸管器件的方法。     

A thyristor protected against di/dt failure at breakover turn-on

The principle and the operation of a thyristor that can be turned on by exceeding its breakover voltage are described. The principle uses the concept of an auxiliary thyristor amplifying the small breakover current to a large gate current for the main thyristor. In this arrangement the breakover turn-on has to occur first in the auxiliary thyristor. This is ensured by a doping of the n-base of the auxiliary thyristor which is higher than that of the n-base of the main thyristor. Time resolved infrared photographs of the breakover turn-on are presented. Also, infrared photographs of the breakdown radiation from p-n-p structures are used to give a survey on the starting silicon which already contains the inhomogeneous doping.     

An optically-coupled crosspoint array with high dv/dt capability and high gate sensitivity

A 2/spl times/4 optically-coupled economical crosspoint array for the telephone speech path with a high breakover voltage (>450 V), high dv/dt capability (>200 V/0.1 /spl mu/s), and high gate sensitivity (<5 mA) is described. This has been achieved by a new device structure with a double-gate MOSFET and RC discharge circuitry formed on a p-n-p-n element. This MOS associated circuitry for dv/dt improvement is referred to as `MAC' p-n-p-n elements with MAC can be separated from each other with a new simple isolation technique called `canal isolation' which facilitates low manufacturing cost. Both p-n-p-n elements and LEDs are bonded face-down on a 44 pin chip carrier ceramic package with bump electrodes which again allows low manufacturing cost. The MAC enables independent control of the dv/dt capability and the gate sensitivity. The authors show the MAC performance in dv/dt improvement and various evaluations of MAC, including computer simulation. High breakover voltage technology and some processes for forming the gate-to-cathode resistor R/SUB GK/ for devices with MAC are discussed. This new optically-coupled crosspoint array with MAC makes possible a high-performance direct interface with conventional telephone sets.     

Novel techniques and procedures for the assessment of fault currentwithstand capability of power thyristors

In applications using high-power thyristors, the designer has to make sure that the selected thyristor will withstand stresses caused by overloads and fault currents. If the surge current characteristics found in the thyristor data sheet do not provide sufficient information, he has to find the transient excursions in junction temperature that will be caused by the worst expected fault current and then make a judgment on whether or not they can be tolerated. The standard way of predicting changes in junction temperature due to a known current waveshape is to determine the corresponding power loss using the on-state (conduction) characteristic and then find the time trace of the junction temperature using the curve of transient thermal impedance. The calculation procedure based on a superposition method has been in use for some 40 years. An improvement based on current state-of-the-art computer software is overdue. However, the main problem facing the designer is that the information found in contemporary data sheets is often neither sufficient for a meaningful calculation nor for deciding whether or not the calculated temperature excursions can be tolerated. This paper deals with three subjects. First, it shows the application engineer how to use off-the-shelf computer software for more accurate and much easier prediction of junction temperature excursions. Second, it advises what to do with the results. Finally, it points to the pieces of information which are needed in the process and which should therefore be found in data sheets of all high-power thyristors. The proposed method for calculation of temperature excursions in high-power thyristors is also applicable to other electrical apparatus such as ZnO arresters, transformers, electric machines, etc     

The forward characteristics of thyristors

A theory on the forward V-I characteristics of P⁺-P-N-P-N⁺thyristors is proposed. Taking the minority carrier lifetime in the base region into account, the effects of the device structures on the forward characteristics are discussed on the following three cases: 1) low-level operation, 2) middle-level operation, and 3) high-level operation. At middle-level operation, the term that is independent of current and, at high-level operation, the √I dependency, appears in the forward characteristics of the thyristors. The general theory is illustrated by reference to experimental results on silicon-controlled rectifiers.     

High dI/dT light-triggered thyristors

Directly light-triggered, 4000- and 6000-V thyristors were designed, fabricated, and tested to obtain high performance in dI/dt, dV/dt, and photosensitivity. Built-in resistors protected both auxiliary stages during high dI/dt turn-on. The novel use of etched moats to define the resistors was compatible with an optical gate structure that gives high dV/dt and good photosensitivity. No additional processing steps were needed to fabricate these devices, as compared to standard light-triggered thyristors. A record value of 1000 A/µs at 60 Hz was measured on a 6000-V thyristor, and 850 A/µs was safely triggered with only 1.8 mW of light. The dV/dt immunity of the photogate structure measured 4000 V/µs, rising exponentially to 80 percent of 4000 V, VDRM. Thyristors triggered by dV/dt were not destroyed. A new model of resistor heating was combined with the first measurements of the current pulses through both built-in resistors to identify the mechanism responsible for occasional burn-out of the second resistor. The failure mechanism was conductivity modulation in the surface of the resistor during its microsecond on-time caused by thermally generated carriers. The test results confirmed the utility of built-in resistors for high dI/dt performance with minimal light power and for nondestructive dV/dt triggering.     

The current pulse ratings of thyristors

This paper describes how the current pulse ratings of thyristors during turn-on spreading can be obtained from the maximum allowable junction temperature based on time-to-failure using a combination of analytical and experimental methods. The instantaneous junction temperature rise of a thyristor is analyzed with the aid of a digital computer. In the calculation of temperature rise, the transient thermal impedance during turn-on spreading is considered. Analyzed results agree with the values obtained directly by an infrared detector. In order to estimate the maximum allowable junction temperature based on time-to-failure, "step-stress capability tests" were conducted. In many cases, it was found that there were modes of both catastrophic and degradation failure. The maximum allowable junction temperature was estimated for the nonrepetitive and repetitive current pulse ratings.     

Increasing the current-handling capability of TIL GTO thyristors up to its limits—II. Experimental

The theoretical analysis and the developed design criteria for TIL GTO thyristors presented in the first part of this study (Paper I) are validated experimentally. The TO-220-packaged, high-voltage (V_DRM = V_RRM = 1000–1500 V) test TIL GTOs had a total cathode area of 8 mm², of which the area of deep-diffused cathode zones amounted to 3.5 mm². The implementation of optimized technological/geometrical ratios for TIL gate-cathode configuration yielded TIL GTO thyristors with a maximum controllable anode current of 55 A, which is the highest value of I_ATO reported thus far in the open literature for this class of GTOs (identical device area and case). All technological factors and physical effects underlying this achievement are analyzed in detail in this work. The current balancing between the two types of elementary p-n-p-n sections (standard and quasi-nonregenerative) constituting the vertical structure of the novel device is checked experimentally and the impact of this peculiar effect on current-handling capability of TIL GTOs is assessed both qualitatively and quantitatively. The boost of I_ATO up to its limits, ultimately dictated by the thermal impedance junction-to-case Z_thj?c TO-220-packages, was accompanied by a significant increase of the peak turn-off gain (10–20) of these devices at higher levels of anode current and by failure-safe operation of TIL GTOs at high commutation frequencies (up to hundreds of kHz) under heavy load conditions. The developed devices possess an excellent turn-on sensitivity and a high immunity to noise (high dV/dt capability). All the results of this work show clearly that sought-for benefits could be obtained by using the optimized double-interdigitated (TIL) gate-cathode pattern in GTO thyristors. The notation used is the same as in Paper I.     

dV/dt Breakdown in power MOSFET's

A model fordV/dtbreakdown in power MOSFET's is proposed. This model allows quantitative analysis ofdV/dtlimitation in power MOSFET circuits. Experimental results show good agreement with theoretical predictions.