SiGe BiCMOS technology for RF circuit applications

SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz).     

A SiGe BiCMOS 24-GHz receiver front-end for automotive short-range radar

This paper presents a fully integrated SiGe BiCMOS 24-GHz receiver front-end implemented for a ultra-wideband automotive short-range radar sensor. The circuit consists of a homodyne I/Q down-converter and a 24-GHz synthesizer. The receiver front-end is able to achieve a power conversion gain as high as 30 dB and a 6-dB noise figure, while preserving high linearity performance thanks to a 1-bit gain control. The frequency synthesizer, which also includes an on-chip loop filter, guarantees a phase noise of −104 dBc/Hz at 1-MHz offset from the 24.125-GHz carrier and a 4.7-GHz tuning range from 20.4 to 25.1 GHz.     

基于标准BiCMOS工艺的1.5Gbit/s调节型共源共栅光接收机

基于IBM 0.18μm SiGe Bi CMOS标准工艺设计实现了一种高速、低功耗的光接收机前端模拟电 路。接收机芯片包括调节型共源共栅 (RGC) 跨阻放大器(TIA)、四级限幅放大器(LA)和 输出缓冲 电路(buffer)。采用高跨导SiGe异质结双极晶体管(HBT)作为输入级的RGC TIA有效隔离了 探测器结电容和输入寄生电容的影响,更好地拓展了光接收机的带宽。仿真结果表明,在1.8V电源电 压供电下,驱动50Ω电阻和10pF电容负载时 ,光接收机前端的跨阻增益为76.67dB带宽为2.1GHz 。 测试结果表明,光接收机前端电路的－3dB带宽为1.2GHz,跨阻增 益为72.2dB,在误码率(BER)为10－9的条件 下,光接收机实现了1.5Gbit/s的数据传输速率。在1. 8V电源电压 下,芯片功耗仅为44mW,芯片总面积为800 μm×370μm。     

A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON

In this paper, we present an integrated 155-Mb/s burst-mode receiver (BMR) for passive optical network (PON) applications. The chip has been designed to receive optical signals over a wide dynamic range (-30 to -8 dBm) and temperature range (-40°C to +85°C). The chip was implemented using a 0.8-μm 35-GHz SiGe BiCMOS technology and occupies an area of 4.3×4.9 mm² with a power consumption of 500 mW from a supply voltage of 5 V (3.3 V for the digital PECL output). In the receiver analog front end, we used a low-noise wide-band transimpedance amplifier followed by a nonlinear gain stage to cover a wide signal range without changing the transimpedance gain. The circuit dynamically adjusts the receiver threshold voltage through a feedback loop, thus optimizing the pulsewidth distortion and canceling the optical as well as the electrical offset voltages     

Programmable SiGe BiCMOS low-pass filter for a multicarrier WCDMA base-station receiver

SiGe BiCMOS low-pass filter for a multicarrier WCDMA base-station receiver is described in this paper. The 4th-order Chebyshev filter with a 0.1-dB passband ripple is designed to drive a high-resolution A/D converter. The −3-dB frequency of the implemented filter can be programmed to four different bandwidths: 2.5, 5, 7.5, and 10 MHz depending on the number of received WCDMA channels. The filter achieves +9.7-dBV in-band IIP3, +20-dBV out-of-band IIP3, and 8.5-nV/√Hz input-referred noise density with 10-MHz bandwidth. The circuit uses a 2.5 V supply and has been fabricated in a 0.25-μm SiGe BiCMOS process.     

A 2.5-GHz eight-phase VCO in SiGe BiCMOS technology

We present a 2.5-GHz voltage-controlled oscillator (VCO) with eight equally distributed phases derived from a 10-GHz LC VCO. Stochastic and static phase errors were obtained by spectrum analyzer measurements in conjunction with an on-chip single-sideband mixer. From the measured phase noise spectrum, we predict an absolute rms jitter contribution of 130 fs in a 2-MHz bandwidth phase-locked loop. A static phase error of less than 0.7/spl deg/ was deduced from the sideband suppression. The eight-phase VCO is tunable from 2.35 to 2.85 GHz and draws 16 mA from a 2.0-V supply. Possible applications include clock and data recovery of a 10-Gb/s signal in a fiber-optic receiver as well as high-precision image rejection receivers and I/Q direct up-converters for radio-frequency applications.     

Product applications and technology directions with SiGe BiCMOS

In this paper, we highlight the effectiveness and flexibility of SiGe BiCMOS as a technology platform over a wide range of performance and applications. The bandgap-engineered SiGe heterojunction bipolar transistors (HBTs) continue to be the workhorse of the technology, while the CMOS offering is fully foundry compatible for maximizing IP sharing. Process customization is done to provide high-quality passives, which greatly enables fully integrated single-chip solutions. Product examples include 40-Gb/s (OC768) components using high-speed SiGe HBTs, power amplifiers compatible for cellular applications, integrated voltage-controlled oscillators, and very high-level mixed-signal integration. It is argued that such key enablements along with the lower cost and higher yields attainable by SiGe BiCMOS technologies will provide competitive solutions for the communication marketplace.     

基于SiGe BiCMOS技术的低功耗23G VCO

A 23 GHz voltage controlled oscillator(VCO) with very low power consumption is presented.This paper presents the design and measurement of an integrated millimeter wave VCO.This VCO employs an on-chip inductor and MOS varactor to form a high Q resonator.The VCO RFIC was implemented in a 0.18μm 120 GHz f_t SiGe hetero-junction bipolar transistor(HBT) BiCMOS technology.The VCO oscillation frequency is around 23 GHz,targeting at the ultra wideband(UWB) and short range radar applications.The core of the VCO circuit consumes 1 mA current from a 2.5 V power supply and the VCO phase noise was measured at around -94 dBc/Hz at a 1 MHz frequency offset.The FOM of the VCO is -177 dBc/Hz.     

Current status and future trends of SiGe BiCMOS technology

The silicon germanium (SiGe) heterojunction bipolar transistor (HBT) marketplace covers a wide range of products and product requirements, particularly when combined with CMOS in a BiCMOS technology. A new base integration approach is presented which decouples the structural and thermal features of the HBT from the CMOS. The trend is to use this approach for future SiGe technologies for easier migration to advanced CMOS technology generations. Lateral and vertical scaling are used to achieve smaller and faster SiGe HBT devices with greatly increased current densities. Improving both the f_T and f_MAX will be a significant challenge as the collector and base dopant concentrations are increased. The increasing current densities of the SiGe HBT will put more emphasis on interconnects as a key factor in limiting transistor layout. Capacitors and inductors are two very important passives that must improve with each generation. The trend toward increasing capacitance in polysilicon-insulator-silicon (MOSCAP), polysilicon-insulator-polysilicon (Poly-Poly), and metal-insulator-metal (MIM) capacitors is discussed. The trend in VLSI interconnections toward thinner interlevel dielectrics and metallization layers is counter to the requirements of high Q inductors, potentially requiring a custom last metallization layer     

Single-wafer process technology: enabling rapid SiGe BiCMOS development

This paper explores the application of single-wafer processing (SWP) tools to rapidly create high-value added, innovative processes technologies, using the example of SiGe BiCMOS process technology development to highlight the unique advantages that SWP provides to rapidly develop a cost-effective and innovative platform. This paper also reviews the unique requirements necessary for SiGe BiCMOS technology development. SWP equipment is shown to be ideally suited to meeting both the technical and schedule requirements for rapidly and efficiently executing a technology development plan. In addition, the flexibility of single-wafer tooling is well suited to a lower volume technology without compromising the ability to modularly scale the SiGe unit process to meet higher volume production requirements.     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

A wideband low-noise amplifier (LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth,the input third intercept point (IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

一种8 Bit 10 GHz SiGe BiCMOS比较器

SiGe BiCMOS提供了性能极其优异的HBT（异质结晶体管）,其ft超过70 GHz,β〉120,高线性,低噪声,非常适合高频领域应用。本文基于SiGe BiCMOS工艺。提出了一种高性能全差分超高速比较器,它由宽带宽前置放大器、改进的主从式锁存器组成。采用3．3v单电压源,比较时钟超过10GHz,差模信号电压输入量程为0．8V,输出差模电压为0．4V,输入失调电压约2．5mV,用于8位两步闪烁式AID转换器。     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

正A wideband low-noise amplifier(LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth, the input third intercept point(IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links

This paper presents the design and measurements of a 25-Gb/s inductorless optical receiver in a 0.25-μm SiGe BiCMOS process for 100-Gb/s (25-Gb/s × 4 lines) Ethernet. As the first stage of the proposed optical receiver, a transimpedance amplifier (TIA) employing a pseudo-differential structure with a feedback resistor incorporates DC offset cancellation (DOC) to enhance the input dynamic range. Cascaded by the improved two-stage limiting amplifiers and a 50-Ω output buffer, the receiver achieves high differential swings. For a bit-error rate (BER) of 10⁻¹² at 25 Gb/s, the measured transimpedance gain, bandwidth, sensitivity, and output swing are 63.17 dBΩ, 20.7 GHz, −10.3 dBm, and 352.7 mV, respectively. The power consumption of the entire receiver is 111.6 mW and the core area of the die is 640 μm × 135 μm.     

A single-chip Zero-IF down-converter in SiGe:C BiCMOS technology for WLAN 802.11a

This paper presents the contamination levels, obtained applying the Equivalent Salt Deposit Density ESDD methodology in nine distribution circuits and five substations, belonging to ELECTRICARIBE S.A. E.S.P., and located in the north area of Barranquilla, the main Colombian Atlantic Ocean port. The paper shows the different study stages such as the sampling places selection and configuration, the ESDD measurement procedures and the results evaluation applying statistical techniques.     

Integrated frequency synthesiser in SiGe BiCMOS technology for 60 and 24 GHz wireless applications

A fully integrated silicon-based frequency synthesiser for 60 and 24 GHz applications is presented. The relative frequency tuning range is 5%, and the total power dissipation is 135 mW at 2.3 V supply voltage. Phase noise at 48 GHz is lower than -98 dBc/Hz at 1 MHz offset over the whole tuning range, which is 8 dB lower than in all previous silicon-based solutions     

应用于TD-LTE的SiGe BiCMOS功率 放大器的设计

针对准第四代无线通信技术TD-LTE中2.570~2.620 GHz频段的应用,设计了一款基于IBM SiGe BiCMOS7WL工艺的射频功率放大器。该功率放大器工作于AB类,采用单端结构,由两级共发射极电路级联构成,带有基极镇流电阻,除两个谐振电感采用片外元件外,其他全部元件均片上集成,芯片面积为(1.004×0.736)mm2。测试结果表明,在3.3 V电源电压下,电路总消耗电流为109 mA,放大器的功率增益为16 dB,输出1 dB增益压缩点为15 dBm。该驱动放大器具有良好的输入匹配,工作稳定。