A Two-Wafer Approach for Integration of Optical MEMS and Photonics on Silicon Substrate

This letter reports a novel two-wafer approach which demonstrates an integration of optical microelectromechanical system (MEMS) devices and photonics on a silicon substrate. The great advantage of this novel wafer bonding scheme is the ability to maintain the optical axis of the optical MEMS device at the same axis as the optical components. The bonded two wafers which are partially processed, which allows for further processing on the wafer after bonding. Thus, the critical alignment issue is resolved for devices requiring precise alignment in x-/y-/z-axis. Individual functionalities of optical MEMS device and optical coupling between silicon waveguide, fibers and ball lens are demonstrated. This technology shows the potential for integrating silicon photonics integrated circuit and MEMS components with reconfiguration functions on a single silicon substrate.      

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip     

圆片级封装的新颖对准技术

对于3D互连、圆片级封装(WLP)和先进的MEMS器件的圆片键合,精密对准是一项关键技术,不同的MEMS,常常包含双面加工处理,而IC和CMOS制造业则只利用单面加工处理步骤,因此,圆片到圆片的对准必须使用设置在键合界面(也就是面对面)中的对准标记。论述了面对面对准方法的主要步骤,最新结果报导,用一种特殊开发的对准系统获得了≤1μm的对准精度。设备主要是为圆片对圆片的对准和键合而设计。     

采用晶圆传送机器人的晶圆预对准方法

针对传统的晶圆预对准控制系统成本高和体积大的不足，设计了基于晶圆传送机器人的晶圆预对准装置，并提出了高效、高精度的晶圆圆心和缺口定位算法。采用交换吸附的方式通过预对准装置一维旋转和晶圆传送机器人空间平移实现晶圆预对准。误差分析及预对准实验研究结果表明，晶圆圆心的定位精度＜50 ，预对准时间为10 s，满足设计要求。     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

New challenges for 300 mm Si technology: 3D interconnects at wafer scale by aligned wafer bonding

A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView^®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 μm. The method uses two top–bottom microscope pairs for observing the alignment keys and a minimal Z-axis travel during wafer alignment procedure. After the alignment procedure, the wafers are secured for subsequent wafer bonding procedures. The alignment process is presented in detail, as well as the integration of such an equipment in high production systems able to run wafers up to 300 mm diameter.     

Effective cleaning process and its influence on surface roughness in anodic bonding for semiconductor device packaging

Wafer cleanliness and surface roughness play a paramount role in an anodic bonding process. Impurities and the roughness on the wafer surface result in unbonded areas which lead to fringes and Newton׳s rings. With an augment in surface roughness, lesser area will be in stroke thus making more pressure and voltage to be applied onto the wafers for better bonding. Eventually it became mandatory to choose the best cleaning process for the bonding technology that can substantially reduce the impurities and surface roughness. In this paper, we investigate the bonding of silicon/oxidized silicon on Pyrex (CORNING 7740) glass with respect to surface roughness and cleanliness of the wafers by performing three renowned cleaning processes such as degreasing, piranha, RCA 1& 2 (SC‐Standard Cleaning 1 and 2) and found that RCA compromises the best between the roughness and cleanliness. Studies were also extended to find out the effects of applied voltage and load on the bonded surface. It was observed for samples cleaned with RCA, an increase of 45% in maximum current and decrease of 75% in total bonding time with the applied load and voltage among all the cleaning techniques used. Three dimensional structures for pressure sensor application were successfully bonded by selecting the appropriate load and cleaning process. Atomic force microscopy analysis was done to investigate the surface roughness on silicon/oxidized silicon and Pyrex glass for different cleaning processes. Scanning electron microscopy and optical imaging were performed on the interface for the surface integrity of the bonded samples.     

Self‐Alignment of Patterned Wafers Using Capillary Forces at a Water–Air Interface

Capillary interactions at a water–air interface were used to align a two‐inch glass wafer to a three‐inch silicon wafer. Flat, smooth silica surfaces were patterned with gold millimeter‐scale borders enclosing micrometer‐scale features. The gold features were rendered hydrophobic through the use of self‐assembled monolayers, the silica was wetted with water, and the wafers were pressed together. The assembly snapped into alignment based upon the minimization of the curvature of the meniscus formed at the water–air interface. The accuracy of this alignment was better than one micrometer. Gravitational energy was used to systematically study the alignment force as a function of pattern parameters. These data can be modeled by interfacial energy theory. These experiments identify a clear set of conditions necessary for the use of this technique for high‐precision alignment.     

Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias

A new wafer-scale three dimensional (3D) integration technique, originally developed for Si, is applied to hybridize InP-based photodiode arrays with Si readout circuits. The infrared (IR) photodiodes consisted of an InGaAs absorption layer grown on the InP substrate and were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits to allow 3D integration in the Si fabrication facility. The finished 150-mm-diameter InP wafer was directly bonded to the SOI wafer and interconnected to the Si readout circuits by through-oxide vias (TOV). A 32 × 32 array with 6-μm pixel size was demonstrated. The 3D integration of InP with Si wafers achieved the smallest pixel size, which is less than a half of that can be achieved using conventional flip-chip bump bonding technique.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the advantages of optical over electrical interconnects for conventional two-dimensional VLSI and wafer-scale-integrated circuits have not been clearly demonstrated, for dense multiwafer WSI or hybrid-WSI three-dimensional architectures, the ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages. While optical waveguides are readily fabricated in the wafer plane, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one method of meeting this criterion. Using optical devices operating at wavelengths beyond the Si absorption cutoff, low-loss through-wafer propagation between WSI circuit planes can be achieved over the distances of interest (≈ 1 mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that >90 percent transmittance can be obtained through p-type silicon. Initial results show a 400-percent source-detector coupling enhancement is obtainable for these optical interconnections using VLSI process-compatible SiO2phase-reversal zone plate lenses.     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

Si/Si键合界面的超声显微成像(英文)

硅/硅键合片在MEMS器件的生产中得到了应用。如果硅片的表面被微观粒子或被污染液体中的残余物所沾污,硅/硅键合界面就会产生空洞。如果这些空洞没有被及时发现,将给后道工序带来严重的问题,并降低成品率。超声显微成像对于不同材料的界面反应非常敏感,对硅/硅界面存在的空洞很容易声学成像。使用超声显微成像能够检测到键合界面存在的空洞,因而可以把有缺陷的硅片在造成进一步的损失之前清除掉。高分辨率的超声显微成像可以辨别出直径5μm的空洞。     

Radiation thermometry of silicon wafers in a diffusion furnace forfabrication of LSI

A radiation thermometry technique suitable for measuring the temperature of silicon wafers in a diffusion furnace has been developed. A principal feature of this technique is that it measures the temperature of wafers that are not in the line of sight of a conventional pyrometer. An optical guide, consisting of two quartz prisms, gives optical access to interior wafers in the load. A measuring wavelength of 0.9 μm is selected since a silicon wafer is opaque and its emissivity does not depend on temperature at this wavelength. The accuracy of the thermometry is examined by comparing the measured value of the pyrometer with that of a thermocouple. The two measured values agree within ±2°C in a steady state. When wafers are being inserted into or drawn out from the furnace, however, an error is caused by the veiling glare at the optical guide and the wafer     

Intermediate wafer level bonding and interface behavior

The paper presents a new silicon wafer bonding technique. The high-resolution bonding pad is defined through photolithography process. Photosensitive materials with patternable characteristics are served as the adhesive intermediate bonding layer between the silicon wafers. Several types of photosensitive materials such as SU-8 (negative photoresist), AZ-4620 (positive photoresist), SP341 (polyimide), JSR (negative photoresist) and BCB (benzocylbutene) are tested and characterized for their bonding strength. An infrared (IR) imaging system is established to examine the bonding results. The results indicate that SU-8 is the best bonding material with a bonding strength up to 213 kg/cm² (20.6 MPa) at bonding temperature less than 90 °C. The resolution of bonding pad of 10 μm can be achieved. The developed low temperature bonding technique is particularly suitable for the integration of microstructures and microelectronics involved in MEMS and VLSI packaging processes.     

Characterization of polycrystalline silicon wafers for solar cells sliced with novel fixed‐abrasive wire

For slicing crystalline silicon ingots, we have developed a novel fixed‐abrasive wire where diamond grit is fixed onto a bare wire by resin bonding. The properties of the wafers sliced using a multi‐wire saw with the fixed‐abrasive wire have been investigated. When compared with the wafers sliced with the loose‐abrasive wire, the slicing speed is improved by approximately 2.5‐fold and the thicknesses of saw‐damage layers are reduced by more than a factor of two. Polycrystalline silicon solar cells have been fabricated for the first time utilizing the wafers sliced with the fixed‐abrasive wire, and the cells with the saw‐damage etching depth of 7 µm have shown photovoltaic properties comparable to those prepared using the wafers sliced with the loose‐abrasive wire and subsequently etched to remove the damage layers up to 15 µm. It has been clarified that wafer slicing using the fixed‐abrasive wire is promising as a next‐generation slicing technique for fabrication of solar cells, particularly thin silicon cells where the wafer thicknesses approach or become less than 150 µm. Copyright © 2010 John Wiley & Sons, Ltd.     

Preparation of silicon-on-gallium arsenide wafers for monolithicoptoelectronic integration

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (≈100 nm) single-crystal silicon layers on oxide coated gallium arsenide wafers for use in optoelectronic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolithic integration of thick, stress sensitive optoelectronic devices on silicon, without compromising the performance of CMOS circuitry which can be fabricated in very thin, compressively strained silicon layers using SOT techniques     

Inverse‐Woodpile Photonic Band Gap Crystals with a Cubic Diamond‐like Structure Made from Single‐Crystalline Silicon

Three dimensional photonic band gap crystals with a cubic diamond‐like symmetry are fabricated. These so‐called inverse‐woodpile nanostructures consist of two perpendicular sets of pores in single‐crystal silicon wafers and are made by means of complementary metal oxide–semiconductor (CMOS)‐compatible methods. Both sets of pores have high aspect ratios and are made by deep reactive‐ion etching. The mask for the first set of pores is defined in chromium by means of deep UV scan‐and‐step technology. The mask for the second set of pores is patterned using an ion beam and carefully placed at an angle of 90° with an alignment precision of better than 30 nm. Crystals are made with pore radii between 135–186 nm with lattice parameters a = 686 and c = 488 nm such that a/c = √2; hence the structure is cubic. The crystals are characterized using scanning electron microscopy and X‐ray diffraction. By milling away slices of crystal, the pores are analyzed in detail in both directions regarding depth, radius, tapering, shape, and alignment. Using optical reflectivity it is demonstrated that the crystals have broad reflectivity peaks in the near‐infrared frequency range, which includes the telecommunication range. The strong reflectivity confirms the high quality of the photonic crystals. Furthermore the width of the reflectivity peaks agrees well with gaps in calculated photonic band structures.     

Effect of nanotopography in direct wafer bonding: modeling and measurements

Nanotopography, which refers to surface height variations of tens to hundreds of nanometers that extend across millimeter-scale wavelengths, is a wafer geometry feature that may cause failure in direct wafer bonding processes. In this work, the nanotopography that is acceptable in direct bonding is determined using mechanics-based models that compare the elastic strain energy accumulated in the wafer during bonding to the work of adhesion. The modeling results are presented in the form of design maps that show acceptable magnitudes of height variations as a function of spatial wavelength. The influence of nanotopography in the bonding of prime grade silicon wafers is then assessed through a combination of measurements and analysis. Nanotopography measurements on three 150-mm silicon wafers, which were manufactured using different polishing processes, are reported and analyzed. Several different strategies are used to compare the wafers in terms of bondability and to assess the impact of the measured nanotopography in direct bonding. The measurement and analysis techniques reported here provide a general route for assessing the impact of nanotopography in direct bonding and can be employed when evaluating different processes to manufacture wafers for bonded devices or substrates.     

低温阳极键合工艺研究

对低温阳极键合特性进行了研究.通过对硅片进行亲水、疏水和表面未处理3 种不同处理方式研究其对键合的影响,键合前将硅片浸入去离子水（DIW）中不同时间,研究硅表面H基和氧化硅分子数量对键合的影响.结果表明经亲水处理的硅片在水中浸泡1 h 的键合效果最佳.并设计了不同烘烤时间下的阳极键合实验,表明在100 °C 下烘烤30 min 可以有效减少气泡的数量和尺寸.由不同工艺条件下得到的键合形貌可知,通过控制硅片表面微观状态可以达到减小或消除键合气泡的目的.