Random addressable 2048×2048 active pixel image sensor

In this paper, we discuss the design, design issues, fabrication, and performance of a 2048×2048 active pixel image sensor in a 0.5-μm standard CMOS process. Each pixel, 7.5×7.5 μm² , consists of three transistors and a photo diode, resulting in a 12-million transistor chip with a die size of 16.3×16.5 mm. The pixel has a nonintegrating direct readout architecture, with a logarithmic light-to-voltage conversion. This allows the array to be fully random accessible, both in space and time. The sensor has eight analog outputs, each with a pixel rate of 4.5 MHz, which implies a maximum frame rate of eight full frames per second. Sub-sampling or windowing makes higher frame rates possible. The yield of the sensor is high if one accepts a small number of bad pixels     

读出电路开窗技术研究

读出电路开窗是红外焦平面和图像传感器读出电路中，用于提高图像帧频降低带宽的重要技术。该技术通过减小读出阵列的窗口尺寸，降低电路读出的数据量，从而提高帧频。介绍了两类主要的开窗模式:异步读出模式和同步读出模式。针对异步读出模式扩展性差、存在竞争冒险的问题，以及同步读出模式占用像元面积和窗口切换速度慢的问题，基于同步读出提出了一种行列控制字架构，并设计了一种用于该架构的可重复单元电路，提高了对不同面阵规格的扩展性。完成了所提出的开窗电路设计和版图设计，并对该电路进行了仿真验证。对比其他方案，文中设计实现了任意位置、最小1×1尺寸的开窗，同时解决了占用像元面积和竞争冒险问题，并提高了窗口切换速度。     

A pipelined temporal difference imager

A 189/spl times/182 active pixel sensor (APS) for temporal difference computation is presented. The temporal difference imager (TDI), fabricated in 0.5-/spl mu/m CMOS process, contains in-pixel storage elements for a previous image frame. Difference double-sampling circuits are used to suppress the fixed pattern noise in both images and to compute the difference between the corrected images. The pixel area occupies 25 /spl mu/m by 25 /spl mu/m (using 0.7-/spl mu/m scalable rules), with fill factor of 30%. A novel pipelined readout technique is described, which is used to improve the accuracy of the temporal difference computation. With this pipelined readout architecture, >8-bit precision for the difference image and low spatial droop across the difference image is achieved. The chip consumes 30 mW at 50 fps from a 5-V power supply.     

A multisampling time-domain CMOS imager with synchronous readout circuit

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The proposed multisampling architecture requires only a single bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The goal is to obtain a time-domain imager with high dynamic range that requires lower number of transistors per pixel in order to achieve higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operate in video mode having 10 bit pixel data resolution. Also, we present analysis of the impact of comparator offset voltage on the fixed pattern noise. The architecture was implemented in an imager prototype with 32 × 32 pixel array fabricated in AMS CMOS 0.35 μm and was characterized for sensitivity, noise and color response. The pixel size is 30 μm × 26 μm and it is composed of an n+/psub photodiode, a comparator and a D flip-flop with a 16% fill-factor.     

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.     

用于H.264/AVC的D级数据重用整数运动估计VLSI结构

本文提出了一种用于H.264/AVC的D级数据重用整数运动估计VLSI结构.提出的结构是在一种固定块尺寸运动估计VLSI结构基础上,利用交叉网络实现变块尺寸的计算,使用多bank的存储器组织方式,使片上存储器的读写规则简单,易于处理不同搜索范围和不同尺寸的视频的运动估计.提出的运动估计结构用Verilog HDL描述,使用HJTC 0.18μm工艺,用Synopsys DC做了逻辑综合.相比现有结构,该结构由于增加片上存储器,因此数据重用率高,大大降低了存储带宽需求;另外数据吞吐率高,能够满足高性能视频编码需求.     

X射线平板探测器背板工艺研究进展

从高像素填充因子、低噪声、高帧频、高空间分辨率及柔性五个方面对近些年X射线平板探测器背板工艺的研究进展进行了综述.通过对研究过程中的材料选择、像素结构和读出电路优化的详细阐述,分析了X射线平板探测器背板工艺的研究现状及改善方向.文章同时从新结构、新材料、电路设计及三维探测设计四个方面给出了X射线平板探测背板技术未来的发展趋势.     

CCD区域倍频读出及其对成像的影响

在某空间项目中,需要使用一款指定的CCD传感器研制一套用于空间成像的CCD摄像机系统,并且要求图像的帧频高于CCD传感器的标准帧频。简单的超频读出CCD会使摄像机的信噪比下降。文中首先分析了CCD摄像机在空间条件下影响成像信噪比的多种原因,发现读出噪声对输出图像的信噪比影响是最大的。使用区域倍频读出方法来提高CCD摄像机的输出帧频,即在图像的水平和垂直方向都使用4倍的时钟读出部分像元。最后把区域倍频读出CCD的图像信号和整体超频读出CCD的图像信号进行了信噪比对比检测,测试结果表明区域倍频读出的CCD图像质量较好。     

A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition

An alternative image decomposition method that exploits prediction via nearby pixels has been integrated on the CMOS image sensor focal plane. The proposed focal plane decomposition is compared to the 2-D discrete wavelet transform (DWT) decomposition commonly used in state of the art compression schemes such as SPIHT and JPEG2000. The method achieves comparable compression performance with much lower computational complexity and allows image compression to be implemented directly on the sensor focal plane in a completely pixel parallel structure. A CMOS prototype chip has been fabricated and tested. The test results validate the pixel design and demonstrate that lossy prediction based focal plane image compression can be realized inside the sensor pixel array to achieve a high frame rate with much lower data readout volume. The features of the proposed decomposition scheme also benefit real-time, low rate and low power applications.      

三维小波变换结合运动补偿的视频编码器

对三雏小波变换结合运动补偿的视频压缩算法提出了改进方案。针对运动补偿提升（MCLIFT）框架的弱点,结合MPEG的特点,采用新的帧结构对视频序列进行帧间滤波去除时间冗余,再对每个帧在空间上进行小波分解并用SPIHT算法对小波系数进行编码。实验表明,此方法继承了MCLIFT框架的优点,同时又减少了时延和所需的帧缓存,而且这种与MPEG相似的帧结构能进一步降低码率,提高压缩比。     

MATIA: a programmable 80 /spl mu/W/frame CMOS block matrix transform imager architecture

In this paper, we introduce our CMOS block MAtrix Transform Imager Architecture (MATIA). This imager is capable of performing programmable matrix operations on an image. The imager architecture is both modular and programmable. The pixel used in this architecture performs matrix multiplication while maintaining a high fill factor (46%), comparable to active pixel sensors. Floating gates are used to store the arbitrary matrix coefficients on-chip. The chip operates in the subthreshold domain and thus has low power consumption (80 /spl mu/W/frame). We present data for different convolutions and block transforms that were implemented using this architecture, and also present data from baseline JPEG and motion JPEG systems which we have implemented using MATIA.     

低噪声CMOS图像传感器技术研究综述

文章总结了低噪声CMOS图像传感器代表性关键技术的最新研究进展。从CMOS图像传感器架构及各模块设计的角度,介绍了有源像素结构和图像传感器架构,分析了广泛采用的像素内源跟随CMOS图像传感器读出电路及其噪声等效模型,重点介绍了低噪声CMOS图像传感器关键技术,包括共享参考像素差分共源放大器技术、相关多采样技术、像素内斩波技术,以及相关技术的电路级实现方式。     

基于H.264快速半像素插值算法的VLSI实现

提出一种快速半像素插值算法的VLSI硬件结构,该结构充分利用中间数据,有效地降低了分像素运动估计的计算量。采用Altera FPGA开发平台进行验证,系统可稳定地工作在135 MHz时钟频率下,并实时编解码1080P@25fps高清视频,满足系统的实时性要求。     

基于分时共享方案的640×512红外读出电路设计

大规模、高集成度的红外焦平面器件是实现高空间分辨率红外成像的核心。针对高集成度的红外焦平面技术发展,文中设计了一款15 m中心距640512的红外焦平面读出电路。为提升器件信噪比和积分时间,提出了一种22四个像元分时复用积分电容共享技术方案,单元采用直接注入（DI）结构作为输入级,使得读出电路最大电荷容量可达20 Me-/像元。电路有两档电荷容量可选,可满足不同光电流信号的读出要求。为了减小噪声的注入及提高缓冲器偏置电流的精度,为信号传输链路设计了相应的偏置电路。电路仿真结果表明,电路帧频108 Hz,功耗低于110 mW,线性度可高达99.99%。电路采用了CSMC 0.18 m 1P4M 3.3 V工艺加工流片,常温测试结果显示电路工作电流正常,偏置开关可控,功能正常。     

Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors

H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching VBS-ME, and compare it with systolic implementations. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. Five different designs, one and two dimensional systolic and tree implementations along with bit-serial, are compared in terms of performance, pixel memory bandwidth, occupied area and power consumption.

高性能低噪声数字读出电路

红外焦平面的数字读出是信息化发展的必然方向,其关键技术是数字读出电路。介绍了数字读出电路的发展现状和主要架构,重点分析了时间噪声和空间噪声的来源和影响,并给出低噪声设计指导。同时对线性度、动态范围和帧频等主要性能进行了讨论,设计了两款数字读出电路。采用列级ADC数字读出架构设计了640×512数字焦平面探测器读出电路,读出噪声测试结果为150 μV,互连中波探测器测试NETD为13 mK。基于数字像元读出架构设计了384×288数字焦平面探测器读出电路,互连长波探测器测试NETD小于4 mK,动态范围超过90 dB,帧频达到1 000 Hz。所设计的两款读出电路有效提升了红外焦平面的灵敏度、动态范围和帧频等性能,表明数字读出电路技术对红外探测器性能的提升具有重要作用。     

A Low Power Architecture for HASM Motion Tracking

This paper proposes low power VLSI architecture for motion tracking that can be used in online video applications such as in MPEG and VRML. The proposed architecture uses a hierarchical adaptive structured mesh (HASM) concept that generates a content-based video representation. The developed architecture shows the significant reducing of power consumption that is inherited in the HASM concept. The proposed architecture consists of two units: a motion estimation and motion compensation units.The motion estimation (ME) architecture generates a progressive mesh code that represents a mesh topology and its motion vectors. ME reduces the power consumption since it (1) implements a successive splitting strategy to generate the mesh topology. The successive split allows the pipelined implementation of the processing elements. (2) It approximates the mesh nodes motion vector by using the three step search algorithm. (3) and it uses parallel units that reduce the power consumption at a fixed throughput.The motion compensation (MC) architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame using affine transformation to warp the texture with different mesh patches. The MC reduces the power consumption since it uses (1) a multiplication-free algorithm for affine transformation. (2) It uses parallel threads in which each thread implements a pipelined chain of scalable affine units to compute the affine transformation of each patch.The architecture has been prototyped using top-down low-power design methodology. The performance of the architecture has been analyzed in terms of video construction quality, power and delay.     

一个128×128CMOS快照模式焦平面读出电路设计

本文介绍了一个工作于快照模式的CMOS焦平面读出电路新结构——DCA(Direct-injection Charge Amplifier)结构.该结构像素电路仅用4个MOS管,采用特殊的版图设计并用PMOS管做复位管,既可保证像素内存储电容足够大,又可避免复位电压的阈值损失,从而提高了读出电路的电荷处理能力.由于像素电路非常简单,且该结构能有效消除列线寄生电容C_bus的影响,因此该结构非常适用于小像素、大规模的焦平面读出电路.采用DCA结构和1.2μm双硅双铝(DPDM-Double-Poly Double-Metal)标准CMOS工艺设计了一个128×128规模焦平面读出电路试验芯片,其像素尺寸为50×50μm²,电荷处理能力达11.2pC.本文详细介绍了该读出电路的体系结构、像素电路、探测器模型和工作时序,并给出了精确的HSPICE仿真结果和试验芯片测试结果.     

Low-power reduced transistor image sensor

An image sensor comprising an array of 128 by 50 super pixels, column parallel current conveyors and global difference double sampling (DDS) unit is presented. The super pixel consists of: a reset transistor, a readout transistor, four transfer transistors and four photodiodes. The photo pixel address switch is placed outside the pixel, effectively implementing 1.5 transistors per pixel using a sharing scheme of the readout and reset transistor. The column FPN of 0.43% from saturated level and SNR of 43.9 dB is measured. The total power consumption is 5 mW at 30 frame/s.     

Dynamic analysis of the nature of nonlinearity of the lighting characteristics of the active pixels of a CMOS image detector

The dynamics of the information-signal readout in active photosensors of modern CMOS image detectors is studied by the methods of mathematical simulation. Under the assumption of a specific (quasicylindrical) shape of the pixel photodiode and with the appropriete application of the exact nonstationary solutions of the 2D diffusion equation, an universal curve of relaxation of the photodiode potential at the signal preset stage and at the readout stage is constructed. An algorithm allowing calculation of the pixel lighting characteristics at any ratio of frame duration and the exposure and readout times is proposed. The corresponding numerical calculation yields the shape of the lighting characteristic close to that observed experimentally. The proposed model explains the anomalously high photosensitivity at small signals by incomplete erasing of the frame exposure at the potential preset stage before the exposure.