共查询到19条相似文献,搜索用时 125 毫秒
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设计了一种面向多媒体处理的8×8可重构处理阵列,并在该阵列基础上,对其粒度进行改进,提出了一种基于亚字并行的改进型可重构阵列设计思路.该设计根据图像处理中的算法的位宽特点,实现了一种数据的高位和低位可以同时运算的可重构阵列单元,有效提高数据的并行度,使得阵列的处理速度得到了显著的提高.在典型的图像处理中,这种改进型可重构阵列的处理能力较原来增加了一倍. 相似文献
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针对目前PC算法无法实现图像实时处理以及固定硬件平台很难实现算法修改或者升级的问题,设计一种基于SOPC可重构的图像采集与处理系统,实现了图像数据的片上实时处理以及在不改变硬件电路结构而完成算法修改或者升级的功能。此系统围绕两块Xilinx FPGA芯片进行设计,通过FPGA以及其Microblaze 32 bit软核处理器和相关接口模块实现硬件电路设计,结合FPGA开发环境ISE工具和EDK工具协作完成软件设计。由于采用SOPC技术和可重构技术,此设计具有设计灵活、处理速度快和算法可灵活升级等特点。 相似文献
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用于可重构计算的FPGA开发平台的研究 总被引:1,自引:1,他引:0
研究了基于PCI总线和多片FPGA的可重构计算平台.采用PCI9054实现PCI总线接口,通过配置桥接FPGA实现计算机与算法FPGA的数据通信,两片算法FPGA用于并行处理数据.桥接FPGA配置灵活,易于多片算法FPGA扩展,算法FPGA并行处理数据效率高,算法设计通用性强.计算机与算法FPGA数据传输达40Mb/ s,算法FPGA实际数据吞吐量为1.28Gb,适合实现视频和音频压缩、数据加密、解密等计算密集型算法. 相似文献
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介绍一种采用多条运算流水线技术的粗粒度动态可重构计算系统.使得能够在时间维和空间维上同时开发算法的循环级并行性。在此基础上研究了可重构器件的细织结构形式以及面向动态可重构的互连网络.并给出了在该系统上求解一般问题(如FIR)的重构与执行过程。最后,为实现算法到结构的自动化映射而初步建立了协同编译器框架并展望了在系统中融合向量技术的前景. 相似文献
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提出了一种基于可重构总线的数据并行体系结构。首先,针对现代多媒体处理中存在的问题,提出了一种基于可重构总线的一维处理单元阵列体系结构;其次,设计各处理单元之间的通信模块以及处理元之间的数据传递方式,即可重构数据总线的设计;最后,通过对几种常用的图像处理算法的验证,表明基于可重构总线的一维SIMD体系结构在逻辑上具有可行性。 相似文献
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H. Blume H.-M. Blüthgen C. Henning P. Osterloh T.G. Noll 《The Journal of VLSI Signal Processing》2002,31(2):117-126
The computational power required in many multimedia applications is well beyond the capabilities of today's multimedia systems. Therefore, the embedding of additional high-performance accelerator multimedia components into these systems is most decisive. This paper presents the embedding of multimedia components into computer systems using reconfigurable coprocessor boards. The goal of those reconfigurable platforms which can be adapted to several applications and which include programmable digital signal processors, control and memory devices as well as dedicated multimedia ASICs is worked out. On the way to such a platform four ASICs for image and text processing are presented. The embedding of these components into a computing system using a CardBus-based coprocessor board is shown. Such a reconfigurable coprocessor board is an important intermediate stage on the way to future hybrid reconfigurable systems on chip. 相似文献
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Budgett D.M. Tang P.E. Sharp J.H. Chatwin C.R. Young R.C.D. Wang R.K. Scott B.F. 《Electronics letters》1996,32(17):1557-1559
A reconfigurable hardware design permits very fast feature extraction from high frame rate video images. By implementing parallel pixel processing paths in programmable gate arrays a wide range of image processing algorithms can be implemented in realtime 相似文献
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针对立方体钠卫星GNC信息处理系统高计算性能与低功率消耗相矛盾的问题,提出了一种资源限制型可重构并行信息处理方法。该方法采用紧耦合可重构并行信息处理架构,将GNC信息处理中需要多次迭代计算且不适合CPU处理的复杂软件算法,以动态部分重构硬件电路单元(DPR)的方式实现,采用基于互斥量的多核并行可重构资源调度算法,通过多核CPU并行管理与调度共享的DPR单元,完成软件算法的硬件加速与优化。实验结果表明,该方法实现了立方星GNC信息处理系统的高效实时快速处理,与传统信息处理方法相比,可节约50%左右的功耗,可应用于计算资源极为有限的星上信息处理领域,具有很好的工程应用前景。 相似文献
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David R. Martinez Tyler J. Moeller Ken Teitelbaum 《The Journal of VLSI Signal Processing》2001,28(1-2):63-83
Many radar sensor systems demand high performance front-end signal processing. The high processing throughput is driven by the fast analog-to-digital conversion sampling rate, the large number of sensor channels, and stringent requirements on the filter design leading to a large number of filter taps. The computational demands range from tens to hundreds of billion operations per second (GOPS). Fortunately, this processing is very regular, highly parallel, and well suited to VLSI hardware. We recently fielded a system consisting of 100 GOPS designed using custom VLSI chips. The system can adapt to different filter coefficients as a function of changes in the transmitted radar pulse. Although the computation is performed on custom VLSI chips, there are important reasons to attempt to solve this problem using adaptive computing devices. As feature size shrinks and field programmable gate arrays become more capable, the same filtering operation will be feasible using reconfigurable electronics. In this paper we describe the hardware architecture of this high performance radar signal processor, technology trends in reconfigurable computing, and present an alternate implementation using emerging reconfigurable technologies. We investigate the suitability of a Xilinx Virtex chip (XCV1000) to this application. Results of simulating and implementing the application on the Xilinx chip is also discussed. 相似文献
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面向DSP应用的可重构计算 总被引:2,自引:2,他引:0
DSP应用的特点是计算密集并适合并行处理,传统的可编程处理器与ASIC在性能和灵活性上各有优劣.因此出现了一种新的计算模式-可重构计算.由于它能将效率和灵活性很好地结合在一起,故正得到广泛的关注和研究.本文在介绍可重构计算的概念和分类的基础上,着重讨论了一些主流的可重构计算系统,分析了各类系统应用于DSP的特点,对可重构计算在计算模型,编译器,映射技术以及开发环境等方面的现状和趋势进行了探讨,并给出了自己的思考. 相似文献
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《Communications Magazine, IEEE》2004,42(5):72-81
Future wireless systems are expected to be characterized by increasing convergence between networks and further development of reconfigurable radio systems. In parallel with this, demand for radio spectrum from these systems will increase, as users take advantage of high quality multimedia services. This article aims to investigate and review the possibilities for the dynamic allocation of spectrum to different radio networks operating in a composite reconfigurable wireless system. The article first looks into the current interest of regulators in this area, before describing some possible schemes to implement dynamic spectrum allocation and showing some example performance results. Following this, the technical requirements that a DSA system would have, in terms of reconfigurable system implementation, are discussed. 相似文献
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红外与可见光图像实时配准融合系统 总被引:13,自引:3,他引:10
描述了一个自主研制的基于实时分布式多处理机的图像配准和融合系统的设计与实现方案。本系统是具有并行计算机体系结构的通用高速实时图像融合处理系统,选择VxWorks实时操作系统和VEM64x总线的软硬件平台,采用AD公司新型的TS101DSP处理器为核心,多DSP处理器分布并行进行处理,完成多源图像实时高速配准和融合需要进行的大量运算,CPLD芯片完成了采集控制以及多传感器视频同步。由于采用了基于高性能DSP的实时嵌入式系统和通用标准化总线结构设计,该系统可以灵活地应用多种配准和融合算法来实现可见光和红外双通道数字图像的高速实时融合处理,比较好地解决多尺度图像配准融合算法的大数据量计算处理与系统实时性要求之间的矛盾,为多传感器实时图像配准融合处理系统的研制奠定了良好的技术基础。 相似文献
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本文介绍了邻域图像处理机原理,提出了邻域图像处理中新型的收缩型和级联型邻域功能流水线结构.这两种邻域功能流水线的流水线作业是以独立的图像处理算法为基础进行的,可以实时(甚至超实时)地完成多个独立的图像处理算法,高度体现了并行处理机数据并行、处理并行的原则,体现了多个算法的有机集成,因此特别适合于实际问题对综合算法的需求.这种邻域功能流水线结构不仅大大提高了图像处理的速度,而且增强了系统的灵活性.本文论述了收缩型和级联型邻域功能流水线的结构,给出了多个图像处理功能的组合. 相似文献