Design and simulation of high-performance lateral bipolar junction transistor on partial buried oxide

In this work, we propose a new structure of a lateral bipolar junction transistor (LAT-BJT) on partial buried oxide (PBOX). The novelty of the proposed LAT-BJT device is the use of PBOX, covering just base and emitter regions only. A two-dimensional (2D) calibrated simulation study of the proposed LAT-BJT device has shown that the proposed LAT-BJT on PBOX’s performance is unique when the PBOX is just covering base and emitter regions. At this length of PBOX, a sharp enhancement in cut-off frequency (f_T) (~10 times higher) is achieved in the proposed LAT-BJT on PBOX in comparison to an LAT-BJT on silicon-on-insulator (SOI). The breakdown voltage of the proposed LAT-BJT on PBOX is double than that of the LAT-BJT on SOI device at this PBOX length. A notable enhancement in current gain (β) is observed in the proposed LAT-BJT on PBOX in comparison to the LAT-BJT on bulk device. To check the performance of the proposed LAT-BJT on PBOX at the circuit level, two inverters have been designed and simulated using the mixed-mode simulations of Atlas simulator. It has been observed that the proposed LAT-BJT on PBOX significantly outperforms the conventional LAT-BJT device in switching performance. A notable improvement of 32% in ON delay and 72.9% in OFF delay is obtained in the proposed LAT-BJT on PBOX device in comparison to the conventional LAT-BJT device.     

A novel TFS-IGBT with a super junction floating layer

A novel trench field stop (TFS) IGBT with a super junction (SJ) floating layer (SJ TFS-IGBT) is proposed.This IGBT presents a high blocking voltage (>1200 V), low on-state voltage drop and fast turn-off capability. A SJ floating layer with a high doping concentration introduces a new electric field peak at the anode side and optimizes carrier distribution, which will improve the breakdown voltage in the off-state and decrease the energy loss in the on-state/switching state for the SJ TFS-IGBT. A low on-state voltage (VF) and a high breakdown voltage (BV) can be achieved by increasing the thickness of the SJ floating layer under the condition of exact charge balance. A low turn-off loss can be achieved by decreasing the concentration of the P-anode. Simulation results show that the BV is enhanced by 100 V, VF is decreased by 0.33 V (at 100 A/cm2) and the turn-off time is shortened by 60%, compared with conventional TFS-IGBTs.     

一种带有超结浮空层的槽栅场阻IGBT

本文提出了一种带有超结浮空层的槽栅场阻IGBT,它具有高的击穿电压(>1200V),低的正向压降和快速的关断能力。高掺杂的 SJ 浮空层在阳极侧引入了电场峰的同时优化了器件内载流子分布,带来关态击穿电压提高,开态、开关态能量损耗减少等好处。在保持电荷平衡的前提下,增加 SJ 浮空层的厚度可以提高击穿电压和降低正向压降,降低 P 型阳极浓度可以减少关断损耗。与传统结构相比,新结构击穿电压提高了100V,正向压降降低了0.33V（电流密度为100A/cm2）,关断时间缩短了60%。     

ESTD: an emitter switched thyristor with a diverter

In this paper we report a 600 V Emitter Switched Thyristor with a Diverter (ESTD) that incorporates a p-channel diverter adjacent to the floating emitter to improve the turn-off capability of the conventional Emitter Switched Thyristor (EST). The current saturation feature of the EST is retained in this new device. Experimental devices show a 27-50% improvement in maximum gate controllable current over the conventional EST for resistive switching, with a small penalty in forward drop     

一种新型的快速关断绝缘栅双极晶体管

本文提出了一种新型的快速关断绝缘栅双极晶体管。在关断的时候,器件用一个自己驱动的P型晶体管来短路发射极PN结。在没有引入如折返电流电压曲线等副作用和工艺困难的情况下,器件实现了低导通压降和快速关断。数值仿真表明关断时间从120ns降到12纳秒,同时并没有增加导通压降。     

具有部分界面等电势浮空埋层的高压SOI PLDMOS

A novel silicon-on-insulator（SOI） high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer（FBL） and its analytical model is analyzed in this paper.The surface heavily doped p-top layers,interface floating buried N⁺/P⁺ layers,and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance.On the condition of ESIMOX（epoxy separated by implanted oxygen）,it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from—232 V of the conventional SOI to—425 V and the specific resistance R_on,sp is reduced from 0.88 to 0.2424Ω·cm².     

A novel lateral IGBT with a controlled anode for on-off-state loss trade-off improvement

New Lateral Insulated-Gate Bipolar Transistor with a Controlled Anode (CA-LIGBT) on Silicon-On-Insulator (SOI) substrate is reported. Benefiting by both of enhanced conductivity modulation effect and high resistance controlled electron extracting path, CA-LIGBT has faster turn-off speed and lower forward drop, and the trade-off between off-state and on-state losses is better than that of state-of-the-art 3-D NCA-LIGBT we presented earlier. As simulation results shown, the ratios of Figure of Merit (FOM) for CA-LIGBT comparing to that of 3-D NCA-LIGBT and conventional LIGBT are 1.45:1 and 59.53:1, respectively. And, the new devices can be created by using an additional Silicon Direct Bonding (SDB). So, from power efficient point of view, the proposed CA-LIGBT is a promised device used in power IC's.     

A novel lateral IGBT with a controlled anode for on-off-state loss trade-off improvement

A new lateral insulated-gate bipolar transistor with a controlled anode(CA-LIGBT) on silicon-on-insulator (SOI) substrate is reported.Benefiting from both the enhanced conductivity modulation effect and the high resistance controlled electron extracting path,CA-LIGBT has a faster turn-off speed and lower forward drop, and the trade-off between off-state and on-state losses is better than that of state-of-the-art 3-D NCA-LIGBT,which we presented earlier.As the simulation results show,the ratios of figure of merit(FOM) for CA-LIGBT compared to that of 3-D NCA-LIGBT and conventional LIGBT are 1.45:1 and 59.53:1,respectively.And,the new devices can be created by using additional silicon direct bonding(SDB).So,from the power efficiency point of view,the proposed CA-LIGBT is a promising device for use in power ICs.     

A 100-V lateral DMOS transistor with a 0.3-micrometer channel in a1-micrometer silicon-film-on-insulator-on-silicon

A novel LDMOS transistor structure with breakdown voltages above 100 V has been fabricated in silicon-on-insulator-on-silicon (SOIS). This structure has been fabrication by silicon direct bonding (SDB) and etch-back to a typical film thickness of 1 μm. The silicon carrier layer (handle) serves as a back-gate electrode, which, under proper bias, improves the transistor characteristics significantly. The effective channel length or basewidth is 0.3 μm. Under these conditions, the drift region becomes the current-limiting element. The physics in the drift region in thin silicon films (⩽1 μm) in the transistor on-state is dominated by the injected electrons from the channel. The limitation of the maximum drain current is given by the quasi-saturation effect. Criteria for the further optimization of SOIS LDMOS transistors are presented     

具有新型缓冲层的IGBT特性研究

为了降低低压场终止型IGBT的工艺难度并改善其关断特性,对注氢场终止型IGBT(PFS-IGBT)的缓冲层进行了研究,引入了传统场终止型IGBT(FS-IGBT)和线性缓变掺杂场终止型IGBT(LFS-IGBT)来与PFS-IGBT作对比。PFS-IGBT的缓冲层通过多次注氢形成,从背面到内部的掺杂浓度依次降低,具有多个浓度峰值,厚度为20~30 μm。FS-IGBT的缓冲层掺杂浓度较高,厚度为5 μm。LFS-IGBT的缓冲层从背面到内部的掺杂浓度呈线性降低,其厚度为20~30 μm。采用Sentaurus TCAD对三种具有不同缓冲层结构的IGBT(600 V/40 A)的特性进行了分析。结果表明,PFS-IGBT通过控制注氢次数、剂量和能量可以获得最优的掺杂分布,器件性能与LFS-IGBT相当,比FS-IGBT拥有更平缓的电流关断波形和更强的短路坚固性。     

Optimization of the base electrode for InGaAs/InP DHBT structures with a buried emitter-base junction

We have optimized the base electrode for InGaAs/InP based double heterojunction bipolar transistors with a buried emitter-base junction. For the buried emitter-base structure, the base metal is diffused through a thin graded quaternary region, which is doped lightly n-type, to make ohmic contact to the p⁺InGaAs base region. The metal diffusion depth must be controlled, or contact will also be made to the collector region. Several metal schemes were evaluated. An alloy of Pd/Pt/Au was the best choice for the base metal, since it had the lowest contact resistance and a sufficient diffusion depth after annealing. The Pd diffusion depth was easily controlled by limiting the thickness to 50?, and using ample Pt, at least 350?, as a barrier metal to the top layer of Au. Devices with a 500? base region show no degradation in dc characteristics after operation at an emitter current density of 90 kA/cm² and a collector bias, V_CE, of 2V at room temperature for over 500 h. Typical common emitter current gain was 120. An f_t of 95 GHz and f_max, of 131 GHz were achieved for 2×4 μm² emitter size devices.     

MEMS-tunable 1.55-/spl mu/m VCSEL with extended tuning range incorporating a buried tunnel junction

We present an electrically pumped and micromechanically tunable InP-based vertical-cavity surface-emitting laser operating in the 1.55-/spl mu/m wavelength range. The current confinement is achieved by a buried tunnel junction. The GaAs-based movable top mirror membrane is fabricated separately, assembled on top of the device, and can be actuated electrothermally. A single mode output power of about 1.7 mW and a tuning range of 28 nm was obtained. By the use of an antireflection coating at the semiconductor-air-interface, we were able to extend the tuning range up to 60 nm as expected from one-dimensional simulations.     

Fabrication of SiC lateral super junction diodes with multiple stacking p- and n-layers

Using epitaxial multiple p-n junction structures of 4H-SiC, lateral super junction diodes were fabricated for the first time. The breakdown voltage of the device was 400 V, which is more than 3/spl times/ higher than the theoretical value calculated for a device with uniformly-doped drift layer (130 V), indicating the effective operation of the super junction structure.     

Influence of a floating plane on effective ground plane inductancein multilayer and coplanar packages

The impact of a floating metal layer on the effective ground plane inductance has been investigated in both multilayer (ground planes) and coplanar (ground conductors) packages. For the multilayer case, both thick and thin film geometries were examined, and the results were compared to a thin film coplanar configuration. It was seen that the floating plane actually increases the ground plane inductance in the multilayer case and decreases the ground plane inductance in the lead frame case. Examining the current density in the floating and ground plane and the ground's partial self-inductance and ground-signal partial mutual inductance give a detailed explanation for this phenomenon     

Characteristics of a new isolated p-well structure using thinepitaxy over the buried layer and trench isolation

An isolated p-well structure for deep-submicrometer BiCMOS LSIs is proposed. The structure consists of a retrograde p-well in an n-type thin epitaxial layer over an n⁺ buried layer, and trench isolation. Latchup characteristics in this CMOS structure and breakdown characteristics of the shallow p-well are studied on test devices. Excellent latchup immunity and sufficient voltage tolerance are obtained with a thin 1-μm epitaxial layer. A CMOS 1/8 dynamic-type frequency divider using this well structure functions properly up to 3.2 GHz at a 2-V supply voltage     

Chirp and linewidth enhancement factor of 1.55 /spl mu/m VCSEL with buried tunnel junction

Chirp characteristics of a 1.55 /spl mu/m vertical-cavity surface-emitting laser (VCSEL) employing a buried tunnel junction are reported for the first time. From the measurements the linewidth enhancement factor /spl alpha//sub H/ is derived and presented.     

An analysis of a waveguide T junction with an inductive post

The authors analyze the T junction with an inductive post, taking its diameter into account for the case where the current distribution is assumed on the surface of the post. A single cylindrical post placed in a T junction improves the impedance matching and compensates the junction discontinuity in a wide frequency band. The effects of the design parameters, such as the diameter of the post and its location, are clarified. The measured return loss is accurately predicted. On the basis of this analysis, an effective design procedure for the T junction is proposed, and the reflection below -30 dB is realized over 4% bandwidth     

Characterization and modeling of flicker noise in junction field-effect transistor with source and drain trench isolation

The flicker or low-frequency noise behaviors of the junction field-effect transistor (JFET) with source and drain shallow trench isolation (STI) regions for planner technology are studied in detail. High noise level is found in the devices with the source and drain isolation and the normalized drain flicker noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated at the oxide/Si interface in the isolation regions and a model is developed to explain the bias dependencies of the noise level and frequency index of the noise spectra. Although a larger low-frequency noise was found in the STI-JFET when compared with the conventional bulk type JFET, it is still an attractive structure for integrating into CMOS technology for low-noise analog applications. The noise level can be further minimized by keeping STI region small and using a better oxidation technique for the STI passivation.     

On an exciton with a spatially separated electron and hole in quasi-zero-dimensional semiconductor nanosystems

The theory of an exciton with a spatially separated electron and hole (the hole is in the quantum dot volume, and the electron is localized at the outer spherical quantum dot-dielectric matrix interface) is developed within the modified effective mass method. The effect of significantly increasing the exciton-binding energy in quantum dots of zinc selenide, synthesized in a borosilicate glass matrix, relative to that in a zinc-selenide single crystal is revealed.     

Short-circuit protection for an IGBT with detecting the gate voltage and gate charge

This paper proposes a new short-circuit protection method for an IGBT. The proposed method is characterized by detecting not only gate charge but also gate voltage of the IGBT. This results in a shorter protection time, compared to the previous method that detects only the gate charge. A real-time monitoring system using an FPGA, A/D converters, and a D/A converter is used for the proposed protection method. Experimental results verify that the proposed method achieves a protection time of 390 ns, which is reduced by 68% compared to the previous method.