ESTD: an emitter switched thyristor with a diverter

In this paper we report a 600 V Emitter Switched Thyristor with a Diverter (ESTD) that incorporates a p-channel diverter adjacent to the floating emitter to improve the turn-off capability of the conventional Emitter Switched Thyristor (EST). The current saturation feature of the EST is retained in this new device. Experimental devices show a 27-50% improvement in maximum gate controllable current over the conventional EST for resistive switching, with a small penalty in forward drop     

A 100-V lateral DMOS transistor with a 0.3-micrometer channel in a1-micrometer silicon-film-on-insulator-on-silicon

A novel LDMOS transistor structure with breakdown voltages above 100 V has been fabricated in silicon-on-insulator-on-silicon (SOIS). This structure has been fabrication by silicon direct bonding (SDB) and etch-back to a typical film thickness of 1 μm. The silicon carrier layer (handle) serves as a back-gate electrode, which, under proper bias, improves the transistor characteristics significantly. The effective channel length or basewidth is 0.3 μm. Under these conditions, the drift region becomes the current-limiting element. The physics in the drift region in thin silicon films (⩽1 μm) in the transistor on-state is dominated by the injected electrons from the channel. The limitation of the maximum drain current is given by the quasi-saturation effect. Criteria for the further optimization of SOIS LDMOS transistors are presented     

Optimization of the base electrode for InGaAs/InP DHBT structures with a buried emitter-base junction

We have optimized the base electrode for InGaAs/InP based double heterojunction bipolar transistors with a buried emitter-base junction. For the buried emitter-base structure, the base metal is diffused through a thin graded quaternary region, which is doped lightly n-type, to make ohmic contact to the p⁺InGaAs base region. The metal diffusion depth must be controlled, or contact will also be made to the collector region. Several metal schemes were evaluated. An alloy of Pd/Pt/Au was the best choice for the base metal, since it had the lowest contact resistance and a sufficient diffusion depth after annealing. The Pd diffusion depth was easily controlled by limiting the thickness to 50?, and using ample Pt, at least 350?, as a barrier metal to the top layer of Au. Devices with a 500? base region show no degradation in dc characteristics after operation at an emitter current density of 90 kA/cm² and a collector bias, V_CE, of 2V at room temperature for over 500 h. Typical common emitter current gain was 120. An f_t of 95 GHz and f_max, of 131 GHz were achieved for 2×4 μm² emitter size devices.     

MEMS-tunable 1.55-/spl mu/m VCSEL with extended tuning range incorporating a buried tunnel junction

We present an electrically pumped and micromechanically tunable InP-based vertical-cavity surface-emitting laser operating in the 1.55-/spl mu/m wavelength range. The current confinement is achieved by a buried tunnel junction. The GaAs-based movable top mirror membrane is fabricated separately, assembled on top of the device, and can be actuated electrothermally. A single mode output power of about 1.7 mW and a tuning range of 28 nm was obtained. By the use of an antireflection coating at the semiconductor-air-interface, we were able to extend the tuning range up to 60 nm as expected from one-dimensional simulations.     

Influence of a floating plane on effective ground plane inductancein multilayer and coplanar packages

The impact of a floating metal layer on the effective ground plane inductance has been investigated in both multilayer (ground planes) and coplanar (ground conductors) packages. For the multilayer case, both thick and thin film geometries were examined, and the results were compared to a thin film coplanar configuration. It was seen that the floating plane actually increases the ground plane inductance in the multilayer case and decreases the ground plane inductance in the lead frame case. Examining the current density in the floating and ground plane and the ground's partial self-inductance and ground-signal partial mutual inductance give a detailed explanation for this phenomenon     

Fabrication of SiC lateral super junction diodes with multiple stacking p- and n-layers

Using epitaxial multiple p-n junction structures of 4H-SiC, lateral super junction diodes were fabricated for the first time. The breakdown voltage of the device was 400 V, which is more than 3/spl times/ higher than the theoretical value calculated for a device with uniformly-doped drift layer (130 V), indicating the effective operation of the super junction structure.     

Chirp and linewidth enhancement factor of 1.55 /spl mu/m VCSEL with buried tunnel junction

Chirp characteristics of a 1.55 /spl mu/m vertical-cavity surface-emitting laser (VCSEL) employing a buried tunnel junction are reported for the first time. From the measurements the linewidth enhancement factor /spl alpha//sub H/ is derived and presented.     

Characteristics of a new isolated p-well structure using thinepitaxy over the buried layer and trench isolation

An isolated p-well structure for deep-submicrometer BiCMOS LSIs is proposed. The structure consists of a retrograde p-well in an n-type thin epitaxial layer over an n⁺ buried layer, and trench isolation. Latchup characteristics in this CMOS structure and breakdown characteristics of the shallow p-well are studied on test devices. Excellent latchup immunity and sufficient voltage tolerance are obtained with a thin 1-μm epitaxial layer. A CMOS 1/8 dynamic-type frequency divider using this well structure functions properly up to 3.2 GHz at a 2-V supply voltage     

An analysis of a waveguide T junction with an inductive post

The authors analyze the T junction with an inductive post, taking its diameter into account for the case where the current distribution is assumed on the surface of the post. A single cylindrical post placed in a T junction improves the impedance matching and compensates the junction discontinuity in a wide frequency band. The effects of the design parameters, such as the diameter of the post and its location, are clarified. The measured return loss is accurately predicted. On the basis of this analysis, an effective design procedure for the T junction is proposed, and the reflection below -30 dB is realized over 4% bandwidth     

Short-circuit protection for an IGBT with detecting the gate voltage and gate charge

This paper proposes a new short-circuit protection method for an IGBT. The proposed method is characterized by detecting not only gate charge but also gate voltage of the IGBT. This results in a shorter protection time, compared to the previous method that detects only the gate charge. A real-time monitoring system using an FPGA, A/D converters, and a D/A converter is used for the proposed protection method. Experimental results verify that the proposed method achieves a protection time of 390 ns, which is reduced by 68% compared to the previous method.     

Characterization and modeling of flicker noise in junction field-effect transistor with source and drain trench isolation

The flicker or low-frequency noise behaviors of the junction field-effect transistor (JFET) with source and drain shallow trench isolation (STI) regions for planner technology are studied in detail. High noise level is found in the devices with the source and drain isolation and the normalized drain flicker noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated at the oxide/Si interface in the isolation regions and a model is developed to explain the bias dependencies of the noise level and frequency index of the noise spectra. Although a larger low-frequency noise was found in the STI-JFET when compared with the conventional bulk type JFET, it is still an attractive structure for integrating into CMOS technology for low-noise analog applications. The noise level can be further minimized by keeping STI region small and using a better oxidation technique for the STI passivation.     

On an exciton with a spatially separated electron and hole in quasi-zero-dimensional semiconductor nanosystems

The theory of an exciton with a spatially separated electron and hole (the hole is in the quantum dot volume, and the electron is localized at the outer spherical quantum dot-dielectric matrix interface) is developed within the modified effective mass method. The effect of significantly increasing the exciton-binding energy in quantum dots of zinc selenide, synthesized in a borosilicate glass matrix, relative to that in a zinc-selenide single crystal is revealed.     

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.     

A concise analytical approach for predicting the voltage and edge peak field profiles of the planar junction with a single floating field limiting ring

A concise analytical approach for predicting the voltage and edge peak field profiles of the planar junction with a single floating field limiting ring is proposed in this paper. From this analysis, the effects of the background doping concentration, junction depth and reversed voltage on the voltage and edge peak field profiles are analysed. The optimal distance between the main junction and the ring junction is also obtained. The analytical results are in excellent agreement with that of the two-dimensional semiconductor device simulator DESSIS-ISE, showing the validity of the approach presented.     

Development of a dual-axis micromachined convective accelerometer with an effective heater geometry

This paper describes the design, fabrication and testing of a dual-axis micromachined convective accelerometer with a diamond-shaped heater. Modification of heater geometry is advantageous because it is simple and ensures enhanced sensitivity without constraining device size or operating power. The diamond-shaped heater induces active heat flow and a sharp temperature gradient around the heater; together these effects provide high sensitivity. When the fabricated convective accelerometer used SF₆ as an enclosed gas medium, its measured sensitivity was 3.5 mV/g when operating power was 7.4 mW and its bandwidth at −3 dB was 25 Hz.     

Ultrafast all-optical switching with an asymmetric Fabry-Perotdevice using low-temperature-grown GaAs: material and device issues

For future telecommunications systems to take full advantage of the optical fiber bandwidth, it will be necessary to have components responding at picosecond speeds. The only way currently known to achieve these speeds is using all-optical switching. By using low-temperature-grown GaAs (LT-GaAs) in a compact asymmetric Fabry-Perot device, we have achieved ultrafast all-optical switching with large bandwidth, high contrast ratio, low insertion loss, and low switching energy. In this paper, we discuss the dependence of the switch performance on the mirror bandwidth and reflectivity, and the LT-GaAs layer thickness and growth conditions. We develop guidelines for the optimization of the device design to maximize the bandwidth and contrast ratio     

EM scattering analysis of a ferrite cylinder by a FD-FD technique with an effective absorbing boundary condition and MEI

Electromagnetic scattering problem of an arbitrarily shaped ferrite cylinder is analyzed based on the finite difference-frequency domain(FD-FD) method with an effective numerical absorbing boundary condition (ABC) and the measured equation of invariance (MEI) on the terminated boundary. Compared with the method of moments (MoM), both the numerical ABC presented in this paper and the MEI result in dramatic savings in computing time and memory requirement for electrically large objects due to the sparsity of the finite difference equation. The absorbing characteristic of this numerical ABC is demonstrated numerically. The accuracy, memory needs and CPU time of the FD-FD with the numerical ABC or the MEI and the MoM are compared and then result in some important conclusions. Besides, the RCS of some ferrite cylinders are presented.     

Formation and study of buried SiC layers with a high content of radiation defects

Protons with energy E=100 keV were implanted with doses ranging from 2×10¹⁷ to 4×10¹⁷ cm^?2 into 6H-and 4H-SiC n-type samples at room temperature. The samples were subjected to various types of postimplantation heat treatment in the temperature range 550–1500°C. The parameters of the samples were studied by measuring the capacitance-voltage and current-voltage characteristics and by analyzing the photoluminescence spectra. Blistering on the surface of the sample is observed after annealing the samples at a temperature of 800°C only after implantation of protons with a dose of ≤3×10¹⁷ cm^?2. A decrease in the resistivity of the compensated layer sets in after annealing at a temperature of ～1200°C and is completed after annealing at a temperature of ～1500°C. A drastic decrease in the photoluminescence intensity is observed after implantation for all types of samples. Recovery of the photoluminescence intensity sets in after annealing at temperatures ≥800°C and is complete after annealing at a temperature of 1500°C.     

半导体激光穴位照射和电针灸治疗股外侧皮神经炎75例疗效比较

目的 :观察激光穴位照射治疗股外侧皮神经炎的疗效。方法 :将 75例患者随机分为 2组 ,治疗组 42例 ,采用激光穴位照射治疗。对照组 3 3例 ,采用常规针灸治疗。结果 :治疗组的痊愈率与对照组相比差别有显著意义 (P <0 .0 5 )。结论 :电针灸治疗股外侧皮神经炎有确切疗效 ,激光穴位照射治疗在此基础上更显著的提高疗效     

A new vertical IGBT structure with a monolithic over-current,over-voltage, and over-temperature sensing and protecting circuit

A new 600 V vertical Insulated Gate Bipolar Transistor (IGBT) structure with monolithically integrated over-current, over-voltage, and over-temperature sensing and protecting functions has been developed to exploit an extremely excellent trade-off characteristic between an on-state voltage drop and turn-off time for the first time. This device can be easily made by the conventional IGBT fabrication process. An accurate and a real-time device temperature detection, as well as a high withstand capability against over-current and over-voltage conditions (short circuit immunity of 30 μsec, clamped collector voltage of 640 V), have been achieved. Furthermore, an excellent trade-off characteristic of 1.40 V as an on-state voltage drop and of 0.18 μsec as a fall time is also obtained