Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

Intrinsic capacitance of lightly doped drain (LDD) MOSFET's is measured by means of a four-terminal method without using any on-chip measurement circuits. The gate-to-drain capacitance Cgdof LDD MOSFET's is smaller than that of conventional MOSFET's in the saturation region. The technique is applied to determine the effective channel length.     

Cut off frequency and transit time analysis of lightly doped drain (LDD) MOSFETs

Analytical model for the transconductance, cut off frequency, transit time and fringing capacitance of LDD MOSFETs is presented with a simple approach. The analysis is carried out considering the LDD device as a conventional MOSFET with a series resistance [Z.-H. Liu et al., Threshold voltage model for submicrometer MOSFETs. IEEE Trans Electron Devices 1993; ED-40: 86–94] and a simple closed form expressions for cut off frequency and transit time is obtained. The total gate capacitance, i.e. the geometric and fringing capacitance, is calculated for both LDD and non-LDD devices and lower fringing capacitance is reported in LDD devices. Lower cut-off frequencies and higher transit time are reported in LDD devices for the same channel length.     

Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor

The LDD structure, where narrow, self-aligned n^-regions are introduced between the channel and the n⁺source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of the n^-dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n^-regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 µm. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 × basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.     

An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices

MOS devices with double diffusion junctions containing Lightly Doped Drain/Source (LDD) regions have been built and analyzed. Comparison of current characteristics of the 2 μ m LDD devices with conventional devices of same channel length indicates that the LDD devices, while displaying relatively good drain current gain, deviate from the MOS transistors in the linear region due to the intrinsic n^? drain/source resistance and thus have lower substrate current due to the reduced hot electron effects. An analytical method is developed where this intrinsic resistance can be extracted from curve fitting of I–V data. Through curve fitting analysis the intrinsic resistance parameter is found to be an inverse function of transistor width as well as being dependent on temperature in the usual $\text{T}{}^{\mathrm{<mtext>3</mtext><mtext>2</mtext>}}$ manner.     

Analysis of electrical characteristics of gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors with different LDD doping concentration

Different drain field architectures have been recently investigated to reduce field-enhanced effects in conventional self-aligned polysilicon thin-film transistor (TFT) architecture, induced by the intense electric fields at the drain junction. Among these, gate overlapped lightly doped drain (GOLDD) architecture has been shown to be effective in reducing the drain field in both on and off states of the TFT, without introducing appreciable series resistance effects. In this paper, we investigate the electrical characteristics, both in the on- and in the off-regime, of GOLDD polysilicon TFTs, made with different LDD doses, by combining experimental data with two-dimensional (2-D) numerical analysis. We also demonstrate that both the on-state and off-state features of the GOLDD structure can be readily understood in terms of a simple, new model, based upon two TFTs series. This is consistent both with the experimental data and the results of full 2-D simulations. This paper not only clarifies the dependence of kink effect, leakage current, and series resistance upon the LDD-doping, but also provides the guidelines to optimize physical parameters of GOLDD TFTs.     

A self-aligned gate lightly doped drain (Al, Ga)As/GaAs MODFET

An asymmetrical lightly doped drain (LDD) (Al, Ga)As/GaAs modulation-doped FET (MODFET) structure with high drain-to-source and drain-to-gate breakdown voltages was fabricated. The LDD structure has a self-aligned lightly doped n^- region between the channel and a heavily doped n⁺ region at the drain, to reduce the electric field and impact ionization. The length of the lightly doped n ^- region on the drain side was varied from 0 to 1 μm. Drain-to-source breakdown voltage BV_ds improved from 4.6 to >10 V while the transconductance g_m remained unchanged. The drain-to-gate reverse breakdown voltage BV _dg increased from ≈7 to >20 V. The two breakdown mechanisms are believed to be independent. The LDD MODFET should find widespread application in circuits requiring high breakdown voltage such as high-speed analog-to-digital converters (ADCs) and microwave power amplifiers     

An analytic I—V model for lightly doped drain (LDD) MOSFET devices

An analytic I-V model for lightly doped drain (LDD) MOSFET devices is presented. In this model, the n^-region is considered to be a modified buried-channel MOSFET device, and the channel region is considered to be an intrinsic enhancement-mode MOSFET device. Combining the models of these two regions, the drain current in the linear/saturation regions and the saturation voltage can be calculated directly from the terminal voltages. In addition, the parameters used in the channel region can be extracted by a series of least square fittings. According to comparisons between the experimental data measured from the test transistors and the theoretical calculations, the developed I-V model is shown to be valid for wide ranges of channel lengths.     

High holding voltage C-MOS technology with lightly doped source and drain regions

This work presents the results of measurements and simulations of n-well C-MOS structures fabricated to study the effect of reduced source-drain doping of p-channel MOSFET's on latchup triggering and holding characteristics. It is shown that lighter dopings, degrading the emitter efficiency of the parasitic p-n-p bipolar transistor, lead to improved latchup resistance that can be conveniently traded off versus the induced decrease of MOSFET transconductance.     

A reliable profiled lightly doped drain (PLD) cell for high-densitysubmicrometer EPROM's and flash EEPROM's

A cell with a profiled lightly doped drain (PLD) structure is proposed for realizing high-density nonvolatile memories in the submicrometer range. The PLD cell has a surface n^- layer with a diffusion self-aligned (DSA) boron layer, in addition to a deep phosphorus n^- layer. This structure enhances hot-electron generation during write and significantly reduces it during read. The cell exhibits improved data retention as a result of reduced band-to-band tunneling leakage current. The optimized PLD cell combines improved soft-write immunity with high read current, and low gate-induced breakdown leakage with high-speed writing. Simulation results and measurements on a fabricated test structure confirm these characteristics     

High-frequency and switching performance investigations of novel lightly doped drain and source hetero-material-gate CNTFET

The effects of lightly doped drain and source (LDDS) and hetero-material-gate (HMG) structure on the static characteristics and switching speed performance for a carbon nanotube field effect transistor (CNTFET) have been theoretically investigated by a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green׳s functions (NEGF) solved self-consistently with Poisson׳s equation. A comparison study of electrical characteristics in conventional single-material-gate CNTFET (C-CNTFET), LDDS-CNTFET, HMG-CNTFET and LDDS-HMG-CNTFET structures has been performed. Simulations show that, compared with the other structures, LDDS-HMG-CNTFET significantly decreases leakage current, subthreshold swing, and increases on/off current ratio. In addition, effects of the gate electrode work function of the LDDS-HMG-CNTFET have been studied theoretically. The results indicate that the electron transport efficiency, and the cutoff frequency of the device, can be optimized by reasonably selecting the gate electrode work function. This work illustrates that the proposed LDDS-HMG-CNTFET might be useful for low-power high-speed CNTFET digital design.     

Carrier mobility in MOSFETs fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrode, and self-aligned source and drain

A study of electron and hole mobilities for MOSFET devices fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrodes and self-aligned source and drain is presented. High effective electron and hole mobilities, 250 cm/sup 2//V/spl middot/s and 70 cm/sup 2//V/spl middot/s, respectively, were measured at high effective field (>0.5 MV/cm). The NMOSFETs have an equivalent oxide thickness (EOT) of 1.3 nm and the PMOSFETs have an EOT of 1.5 nm. The effect of interface engineering on the electron and hole mobilities is discussed.     

Design for suppression of gate-induced drain leakage in LDD MOSFETsusing a quasi-two-dimensional analytical model

A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 10¹⁴/cm², the LDD and fully overlapped LDD devices exhibit similar GIDL current     

Characteristics of a buried-channel graded drain with punchthrough stopper (BGP) MOS device

MOS device structures having a graded-drain (G), a buried-channel (B), and a punchthrough stopper (P) are realized by a triimplantation technique without additional masking. Combined effects of B, G, and P are experimentally investigated. Significant improvements in source-to-drain (S-D) breakdown voltage and the short-channel effect are observed in a BGP device. The BGP device structure will be durable for 5-V operation in the coming VLSI era.     

增强型自对准源漏区AlN/GaN/AlN 氮极化金属绝缘半导体场效应晶体管的静态特性与短沟道效应的研究

This paper aims to simulate the I–V static characteristic of the enhancement-mode(E-mode) Npolar Ga N metal–insulator–semiconductor field effect transistor(MISFET) with self-aligned source/drain regions.Firstly, with SILVACO TCAD device simulation, the drain–source current as a function of the gate–source voltage is calculated and the dependence of the drain–source current on the drain–source voltage in the case of different gate–source voltages for the device with a 0.62 m gate length is investigated. Secondly, a comparison is made with the experimental report. Lastly, the transfer characteristic with different gate lengths and different buffer layers has been performed. The results show that the simulation is in accord with the experiment at the gate length of 0.62 m and the short channel effect becomes pronounced as gate length decreases. The E-mode will not be held below a100 nm gate length unless both transversal scaling and vertical scaling are being carried out simultaneously.     

多晶硅薄膜晶体管源漏轻掺杂结构的优化设计

应用场助热电子发射(thermionic field emission)模型合理地分析了多晶硅薄膜晶体管中显著漏电流与器件参数及电极电压等因素间的内在关系,讨论了源漏轻掺杂结构在抑制漏电流方面的物理机制,并给出轻掺杂结构参数(如轻掺杂浓度、轻掺杂区域长度等)的优化设计,为多晶硅薄膜晶体管的器件设计提供了可靠的理论依据.     

多晶硅薄膜晶体管源漏轻掺杂结构的优化设计

应用场助热电子发射(thermionic field emission)模型合理地分析了多晶硅薄膜晶体管中显著漏电流与器件参数及电极电压等因素间的内在关系,讨论了源漏轻掺杂结构在抑制漏电流方面的物理机制,并给出轻掺杂结构参数(如轻掺杂浓度、轻掺杂区域长度等)的优化设计,为多晶硅薄膜晶体管的器件设计提供了可靠的理论依据.     

Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

The LDD structure, where narrow, self-aligned n/sup -/ regions are introduced between the channel and the n/sup +/ source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of then- dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n- regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 /spl mu/m. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 X basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.     

Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application

A new stacked-nanowire device is proposed for 3-dimensional (3D) NAND flash memory application. Two single-crystalline Si nanowires are stacked in vertical direction using epitaxially grown SiGe/Si/SiGe/Si/SiGe layers on a Si substrate. Damascene gate process is adopted to make the gate-all-around (GAA) cell structure. Next to the gate, side-gate is made and device characteristics are controlled by the side-gate operations. By forming the virtual source/drain using the fringing field from the side-gate, short channel effect is effectively suppressed. Array design is also investigated for 3D NAND flash memory application.     

Schottky barrier thin-film transistor (SBTFT) with silicidedsource/drain and field-induced drain extension

A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from low on-off current ratio, the new device exhibits high on/off current ratio up to 10⁶ for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS process integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications