PXIe多通道数字化仪模块的设计

介绍了一种基于PXIe总线多通道数字化仪模块的总体设计方案.该数字化仪模块采用四片250MSa/s、16位ADC与FPGA做为数据采集控制与信号处理核心单元,实现四个通道并行数据采集存储功能.模块采用PXIe总线接口,利用DMA模式实现主控单元与采集单元的高速数据传输,开发了基于QT的软面板及驱动程序,既保证了模块跨平...     

SOI CMOS Implementation of a Multirate PSK Demodulator for Space Communications

A low-power phase-shift keying demodulator integrated circuit (IC) has been implemented using silicon-on-insulator CMOS technology for deep space and satellite applications. The demodulator employs double differential detection to increase its robustness to the Doppler shift caused by the movement of the space vehicle and sampling technique with 1-bit analog-to-digital converter (ADC) at the front to reduce the complexity and power dissipation. In particular, digital decimation is used after sampling to achieve a low power implementation of multirate transmission. Operating at ultra-high-frequency (435 MHz), the receiver system supports a wide range of data rates (0.1-100 Kbps). From test results, the power consumption of the demodulator circuit including the 1-bit ADC is below 1 mW for data rates up to 100 Kbps     

On a Speech Multiple System Implementation for Speech Synthesis

This paper proposes a voice synthesizer to convert a single speech to multiple speeches. Pitch is an important voice characteristic of speech parameter and it is produced by the periodic vibration of the vocal-cords; the parameter most sensitive for human’s auditory sense. So if you change the pitch of the voice with several different scaling rates, you can produce several different voices at the same time with a voice. The Multiple-Speech Synthesizer will be used in diverse practical applications. The cheer synthesizer that makes group voice from a single voice would be such an example. You could also use the system for a troll toy, birthday song tracks, effect sounds in movies and plays, protection systems of houses, etc. Furthermore, the synthesizer could be used to imitate the voice of famous entertainers or cartoon characters, such as the Mask-man.

DVB-T中多速率DDC的设计与FPGA实现

针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.     

Electronic Implementation of Multirate Sigma-Delta Modulators Using CMOS Technologies

Multirating has been recently proposed to reduce the frequency rate of the first integrator(s) of a single-loop, or the first stage(s) of a cascade, Sigma-Delta modulator (SDM). This is a promising technique for the design of high speed, low-power modulators, as the first integrator (or stage) in the chain primarily determines the performances of the modulator, as well as its power consumption. This paper presents the first implementation of a 2nd-order multirate SDM, showing different circuit solutions. The experimental results obtained with a prototype in a standard 0.6 μm CMOS technology shows that different clock rates can be selected for each integrator of a SDM. Alfredo Pérez Vega-Leal was born in Seville, Spain. He received the Telecommunications Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2003, respectively. Since 1995, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, as research student and became an Associate Professor in 1999. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion. Francisco Colodro was born in Peal de Becerro (Jaén), Spain, in 1968. He received the Ingeniero de Telecomunicación degree from the University of Vigo, Vigo, Spain, in 1992, and the Ph.D. degree from the University of Sevilla, Sevilla, Spain, in 1997. In 1992 he joined the Department of Electronics Engineering, University of Sevilla, where he is currently and Associate Professor. His research interests are in the architectural study of Σ Δ modulators, the implementation of ADCs based on Σ Δ modulators, and application of electronic circuits and systems to communication. Marta Laguna was born in Seville, Spain. She received the Telecommunications Engineering degree from the University of Seville in 2002. She is currently working toward the Ph.D. degree. Her doctoral work focuses on the design of continuous-time sigma-delta modulators. Since 2001, she has been with the Department of Electronic Engineering, School of Engineering, University of Seville, as research student and became an assistant teacher in 2004. Her research interests are high-speed analog-to-digital converters and sigma-delta modulators. Antonio Torralba (M'89–SM'02) was born in Sevilla, Spain, in 1960. He received the electrical engineering and Ph.D. degrees from the University of Sevilla in 1983, and 1985, respectively. Since 1983 he has been with the Department of Electronics Engineering, School of Engineering, University of Sevilla, where he has been Associate Professor in 1987, and Full Professor since 1996, leading a research group on mixed signal design. In 1999 he made a short stay at the Department of Electrical Engineering, NMSU, and he is presently in the Department of Electrical Engineering, TAMU for a Sabbatical stay. His interests include low-voltage analog circuits and systems, analog to digital conversion, Σ Δ modulators, and electronic circuits and systems with application to control and communication. In these fields he has published around 40 journal papers and more than 100 conference papers, and he holds 2 international patents.     

一种语音信号处理平台的设计与实现

为了满足语音信号处理算法实时实现研究的需要,提出了一种以TMS320VC5402为核心的语音处理平台的设计方案。该平台包括JTAG接口电路、闪速(FLASH)存储器的扩展电路、语音采集和语音输出电路,并提供相应电路的硬件实现。目前该平台可以很方便地实现数字滤波、语音增强、语音识别等语音信号处理算法,为研究语音信号算法的实时处理奠定了基础。     

LXI总线数字化仪模块设计

介绍了一种基于LXI总线数字化仪模块的总体设计方案。该数字化仪模块以FPGA和DSP作为采集控制和信号处理核心单元,兼容两种标准频率中频信号的采集与数据处理,采用基于IEEE1588精密时钟协议提供的时间基准进行精确定时触发。软件系统在WindowsNT平台上实现,开发了基于Lab Windows/CVI的虚拟仪器软面板,保证了模块运行的稳定性和人机界面的友好。本数字化仪模块的特点在于该模块在高性能FPGA的控制下实现两种中频信号采集,最高采样频率可达130MHz,可靠性、稳定性好,具有较好的实用价值。     

VLSI Implementation of an Adaptive Multiuser Detector for Multirate WCDMA Systems

A multirate receiver for WCDMA systems based on the adaptive signature method was designed and implemented. We employed an adaptive signature algorithm to consider two well-known multirate schemes, namely, the low rate and the high rate detector for variable spreading factor systems. In monorate scenarios, numerical experimentations showed that the adaptive signature method outperforms the Rake receiver and reaches the performances of the soft 4-stage multistage parallel interference cancellation receiver. In multirate scenarios, the performance comparison of two multirate schemes in floating-point and fixed-point was analyzed. Reusing the existing hardware architecture previously developed for monorate systems, we targeted the hardware implementation of these two multirate schemes on FPGA components.     

多带激励语音编码的实现

随着信息社会的快速发展,通信信道资源变得非常宝贵,各种语音压缩编码技术应运而生.低速率语音编码已成为数字通信中的一个重要的研究领域.多带激励声码器在2.4～4.8 Kb/s速率上能合成出音质比传统声码器好得多的语音,而且具有较好的自然度和容忍环境噪声的能力.MBE声码器作为主要研究对象,从语音分析和语音合成方面对算法做了细致的研究与实现.同时,静音检测算法应用到MBE声码器中,进一步降低了编码速率.最后,通过对仿真结果的分析,针对MBE编码算法的几点不足提出了相应的改进方法.     

大容量数字语音时间记录仪的实现

介绍了自行研制的一种基于DSP和CF卡的大容量双通道数字语音时间记录仪。阐述了系统的硬、软件设计及其功能与工作过程，给出了实际测试指标，最后介绍了该方案在铁路调度系统中的应用。     

15.2kb／sLD—CELP语音编码算法及实时实现

本文以Ｇ．７２８语音编码标准为基础,提出一个１５．２ｋｂ／ｓ ＬＤ－ＣＥＬＰ语音编码算法。通过对滤形码书进行重新设计,降低了算法复杂性,同时保持高质合成语音。最后,用双片ＴＭＳ３２０Ｃ３１高速ＤＳＰ系统全双工实时实现了该算法。     

传声器阵列语音数据采集系统的设计与实现

介绍了一种传声器阵列语音数据果集系统的软硬件设计方案,该系统采用USB2.0接口实时传输采集到的多通道语音数据,系统具有使用方便、容易扩展等特点.     

一种无线语音混沌保密通信系统的设计与实现

为了实现对混沌加密语音信号的无线传输和解密回放,在由DSP芯片TMS320VC5509A、无线射频芯片nRF24L01和音频编解码芯片TLV320AIC23构成的系统硬件平台上,采用Euler算法对连续Lorenz混沌系统进行离散化处理,产生出用于加密和解密的混沌数字序列。对加密后的语音信号进行了无线传输的实验,接收端能够将收到的加密语音信号解密回放,实现了语音信号的无线混沌保密通信。     

Multirate Clos networks

Clos networks are a class of multistage switching network topologies that provide alternate paths between inputs and outputs, making it possible to minimize or eliminate the blocking that can otherwise occur in such networks. In his seminal paper in the Bell System Technical Journal in 1953, Charles Clos showed how these networks could be configured to make them nonblocking and effectively launched the systematic study of switching system performance, a field that has developed a rich technical literature, and continues to be very active and of continuing practical importance. This article describes how Clos' results have been generalized to systems that support connections with varying bandwidth requirements. These generalizations have extended the application of Clos networks well beyond their original technological context and have led to a number of interesting new results, especially in connection with systems that support multicast communication.     

Multirate SPAMM tagging

Many magnetic resonance tagging sequences rely on periodicity in order to produce a uniform tagging grid that covers the whole image plane. This, however, is not always desirable, since motion may be restricted to specific parts of the image, and also different motion characteristics may call for different tagging grid densities. In this paper, we present a combination of the spatial modulation of magnetization 1-1 method with selective excitation pulses that can be used in order to restrict the tagging grid only to regions of interest and produce tagging grid of different density in each region. The method is fast and easy to implement even on older or less expensive systems, since it does not require extensive gradient switching.     

EVRC语音编解码算法的研究及实现

介绍了一种广泛应用于码分多址(CDMA)系统中的EVRC(增强型变速率编解码)原理,着重分析了该算法的关键技术:噪声抑制、参数估计、速率判决等,并对该算法进行了浮点C代码仿真。仿真结果表明,EVRC算法能在较低的平均编码速率下获得高质量的合成语音。     

语音增强算法的研究与实现

语音增强算法也被称为噪声消除算法,在通信行业快速发展的现代社会,语音增强技术具有现实研究意义.首先介绍了算法的运行环境,即语音和噪声信号的特征.其次,对三种经典算法的原理、重要参数和运行框图进行了理论分析.最后以基于统计模型的语音增强算法作为例子进行仿真,验证了语音增强效果.     

语音增强算法的FPGA实现

介绍了语音增强谱减算法的原理,设计并实现了基于FreeDev公司Altera CycloneⅡ开发板的FPGA语音增强谱减算法片上实时系统。系统使用Altera提供的SOPC Builder及IP核进行硬件系统设计,在NiosⅡIDE开发环境下编写软件工程。实验结果表明,采用FPGA实现语音增强算法系统是有效的。