A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ?m² six-transistor bitcell that supports a broad range of operating voltages for low-power and high-frequency embedded applications. The tileable 128 kb SRAM subarray achieves 72% array efficiency with 4.2 Mb/mm² bit density, and consumes 5 mW of leakage power at the supply voltage of 1 V. The design provides 4 GHz and 2 GHz of operating frequencies at the supply voltages of 1.0 V and 0.8 V, respectively. The integrated power management scheme features close-loop memory array leakage control, floating bitline, and wordline driver sleep transistor, resulting in a 58% reduction in subarray leakage power consumption.     

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mum² 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.     

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local dc level control (LDLC) for SRAM cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and fabricated a 32-kB 1-port SRAM using 90-nm CMOS technology. The six-transistor SRAM cell size is 1.25 /spl mu/m/sup 2/. Evaluation shows that the standby current of 32-kB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.     

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

This paper describes an 8 Mb SRAM test chip that has been designed and fabricated in a 45 nm Silicon-On-Insulator (SOI) CMOS technology. The test chip comprises of sixteen 512 kb instances and is designed for use as the principal compilable one-port embedded-SRAM block in a 45 nm ASIC library. Challenges associated with SRAM cell design in SOI are overcome and resulted in a cell size of 0.315 mum² . The paper introduces two circuit techniques that address the AC and DC power consumption issues facing today's embedded-SRAMs. The first technique addresses AC power dissipation by utilizing a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 68% improvement in read power under constant voltage and frequency compared to the previous generation macro . The second technique addresses the DC power consumption by introducing a single-device, header based dynamic leakage suppression scheme that reduces total macro leakage power by 38% with no wake-up cycle requirements.     

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access time at 2 GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support and 128-row refresh to tolerate short refresh time. Cell is 2X denser than SRAM and is voltage compatible with logic.     

A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

An on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed. This SRAM supports three operating modes - high-speed active mode, low-leakage low-speed active mode, and standby mode - and uses a subdivisional power-line control (SPC) scheme. The combination of three operating modes and the SPC scheme realizes low-power operation under actual usage conditions. It operates at 300 MHz, with leakage of 25 /spl mu/A/Mb in standby mode, and 50 /spl mu/A/Mb at the low-leakage active mode. This SRAM also uses a self-bias write scheme that decreases of minimum operating voltage by about 100 mV.     

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer's foot voltage enable sub-T4 write and read without degrading the bit-cell's density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power.     

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 $mu{hbox{A}}$ bit-line leakage current.      

Stability and leakage characteristics of novel conducting PMOS based 8T SRAM cell

The stability and leakage power of SRAMs have become an important issue with scaling of CMOS technology. This article reports a novel 8-transistor (8T) SRAM cell improving the read and write stability of data storage elements and reducing the leakage current in idle mode. In read operation, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In write operation, a negative bias on the cell facilitates to change contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates 2× higher read stability while bearing 20% better write-ability at 1.2 V typical condition and a reduction by 45% in leakage power consumption compared to the standard 6T cell. Results of the bit-cell architecture were also compared to the dual-port 8T SRAM cell. The stability enhancement and leakage power reduction provided with the proposed cell are confirmed under process, voltage and temperature variations.     

Sub-1V embedded SRAM with bit-error immune dual-boosted cell technique

A sub-1 V operating SRAM based on the dual-boosted cell technique is described. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin (SNM) to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell readout current. A 0.18 mum 256 kbit SRAM macro has been fabricated with the proposed technique, which demonstrated: 0.8 V operation with 50 MHz while consuming a power of 65 muW/MHz; 400 mV read SNM at 0.8 V power supply; and a reduction by 87% in bit-error rate compared with that of a conventional SRAM     

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.     

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 x 36 mum² using 65 nm technology.     

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.     

Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology

In this paper the impact of gate leakage on 7T static random access memory (SRAM) is described and three techniques for reducing gate leakage currents and sub threshold leakage currents are examined. In first technique, the supply voltage is decreased. In the second techniques the voltage of the ground node is increased. While in third technique the effective voltage across SRAM cell Vd = 0.348V and Vs = 0.234V are observed. In all the techniques the effective voltage across SRAM cell is decreased in stand-by mode using a dynamic self controllable voltage level (SVL) switch. Simulation results based on cadence tool for 45 nm technology show that the techniques in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node voltage is increased. Result obtained show that 437 FA reductions in the leakage currents of 7T SRAM can be achieved.     

An Experimental 0.8 V 256‐kbit SRAM Macro with Boosted Cell Array Scheme

This work presents a low‐voltage static random access memory (SRAM) technique based on a dual‐boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read‐out current. A 0.18 µm CMOS 256‐kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 µW/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.     

一种全nMOS SOI晶体管4管静态存储器单元

提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管. 存取管的沟道长度小于下拉管的沟道长度. 由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑“1" . 存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的“读”操作. 背栅反馈同时增强了SRAM单元的静态噪声容限(SNM). 该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积. 对SRAM单元的读写速度和功耗做了仿真和讨论. 该SRAM单元可以工作在0.5V电源电压下.     

一种全nMoS SOI晶体管4管静态存储器单元

提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管.存取管的沟道长度小于下拉管的沟道长度.由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑"1".存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的"读"操作.背栅反馈同时增强了SRAM单元的静态噪声容限(SNM).该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积.对SRAM单元的读写速度和功耗做了仿真和讨论.该SRAM单元可以工作在0.5V电源电压下.     

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.     

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral-differential (PID) loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL lock range is 500 MHz to 8 GHz at 1.3 V and 25degC, and 90 MHz to 1.2 GHz at 0.5 V and 100degC. The IC dissipates 8 mW/GHz at 1.2 V and 1.6 mW/GHz at 0.5 V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 ps rms. The phase noise under nominal operating conditions is 112 dBc/Hz measured at a 10 MHz offset from a 4 GHz center frequency. The total circuit area is 200 mum 150 mum.     

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save the power consumption of the cell. This shaped wordline pulse results in improved read noise margin without any degradation in access time for small wordline load. The improvement is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during the hold mode, for a short time (depending on the size of boosting capacitance), wordline voltage becomes negative and charges up to zero after a specific time that results in a lower leakage current compared to conventional SRAM. The proposed technique results in at least 2× improvement in read noise margin while it improves write margin by 3× for lower supply voltages than 0.7 V. The leakage power for the proposed SRAM is reduced by 2% while the total power is improved by 3% in the worst case scenario for an SRAM array. The main advantage of the proposed wordline driver is the improvement of dynamic noise margin with less than 2.5% penalty in area. TSMC 65 nm technology models are used for simulations.