Differential current switch logic: a low power DCVS logic family

Differential current switch logic (DCSL), a new logic family for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL circuits are capable of implementing high complexity high fan-in gates without compromising gate delay. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit. Three forms of DCSL circuits have been developed with varying benefits in speed and power. SPICE simulations of circuits designed using the 1.2 μm MOSIS SCMOS process indicate a factor of two improvement in speed and power over comparable DCVS gates for moderate tree heights     

Design and application of pipelined dynamic CMOS ternary logic andsimple ternary differential logic

Dynamic CMOS ternary logic circuits that can be used to form a pipelined system with nonoverlapped two-phase clocks are proposed and investigated. The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings. A circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed, and an optimal procedure is developed. An experimental chip has been fabricated in a 1.2-μm CMOS process and tested. A binary pipelined multiplier has been designed, using the proposed dynamic ternary logic circuits in the interior of the multiplier for coding of radix-2 redundant positive-digit number. The structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier. The advantages of the circuits over other dynamic ternary logic circuits are shown     

A fully compensated active pull-down ECL circuit withself-adjusting driving capability

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 μm SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF     

Low-voltage dynamic BiCMOS CLA circuit with carry skip using novelfull-swing logic

This paper presents novel low-voltage dynamic BiCMOS logic gates and an improved carry look-ahead (CLA) circuit with carry skip using these new dynamic BiCMOS topologies. The well-known “MOS clock feedthrough effect” is used to achieve full swing with substantially reduced low-to-high evaluation delay in the logic gates, thus, resulting in reduced carry propagation/bypass delay in the cascaded CLA array. Simulations at clocking frequency of 100 MHz, using 2-μm BiCMOS process parameters and supply voltage in the range of 2-4 V displays lower gate delay and lower power dissipation compared to other recent dynamic BiCMOS logic topologies. The circuit has no dc power dissipation, race, or charge redistribution problems. An 8-b CLA with 5-b carry skip was achieved in 2.917 ns. This speed is significantly higher than other recent dynamic BiCMOS CLA designs. In addition, the new CLA circuit is more compact compared to previous dynamic BiCMOS CLA designs. A tiny chip was fabricated using the MOSIS Orbit Analog 2-μm V-well CMOS process for the experimental verification of the new low-voltage dynamic BiCMOS topologies     

Adiabatic dynamic logic

With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice, the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. A chain of 1000 ADL inverters has been constructed in 0.9 μm CMOS and successfully tested at 250 MHz. This result, together with comprehensive circuit simulation, suggest that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry     

Charge recycling differential logic (CRDL) for low powerapplication

A novel logic family, called charge recycling differential logic (CRDL), has been proposed and analyzed. CRDL reduces power consumption by utilizing a charge recycling technique with the speed comparable to those of conventional dynamic logic circuits. It has an additional benefit of improved noise margin due to inherently static operation. The noise margin problem of true single-phase-clock latch (TSPC) is also eliminated when a CRDL logic circuit is connected to it. Two swing-suppressed-input latches (SSILs), which are introduced for use with CRDL, have better performance than the conventional transmission gate latch. Moreover, a pipeline configuration with CRDL in a true two-phase clocking scheme shows completely race-free operation with no constraints on logic composition. Eight-bit Manchester carry chains and full adders were fabricated using a 0.8 μm single-poly double-metal n-well CMOS technology to verify the relative performance of the proposed logic family. The measurement results indicate that about 16-48% improvements in power-delay product are obtained compared with differential cascode voltage switch (DCVS) logic     

Design and implementation of differential cascode voltage switchwith pass-gate (DCVSPG) logic for high-performance digital systems

In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type of ratioless circuit, and it also provides superior performance with less power dissipation and better silicon area tradeoff. The basic DCVSPG design technique, the methodology for optimization, and synthesis of the pass-gate logic tree are described. The standard cell library development taking advantage of the dual-rail outputs of DCVSPG gates is also discussed. The performance comparisons with other existing pass-gate circuit techniques [complimentary pass-transistor logic (CPL), double pass-transistor logic (DPL), and swing restored pass-transistor logic (SRPL)] are presented. For more robust design, the DCVSPG with inverter buffers is also the best choice. A Viterbi macro design using the DCVSPG circuit technique is demonstrated. The process that the design is based upon is a 0.5-μm CMOS technology with 0.25-μm effective channel length and five layers of metal. This macro can run up to 500 MHz at the nominal process condition. In comparison with other existing dynamic circuit techniques, the results also clearly show that the dynamic DCVSPG has the superior power-delay performance     

高性能微处理器中一种改进的高扇入多米诺电路设计与实现

设计实现了一种改进的高扇入多米诺电路结构.该电路的nMOS下拉网络分为多个块,有效降低了动态节点的电容,同时每一块只需要一个小尺寸的保持管.由于省去了标准多米诺逻辑中的尾管,有效地提升了该电路的性能.在0.13μm工艺下对该结构实现的一个64位或门进行模拟,延迟为63.9ps,功耗为32.4μw,面积为115μm2.与组合多米诺逻辑相比,延迟和功耗分别降低了55%和38%.     

Evaluation of three 32-bit CMOS adders in DCVS logic for self-timedcircuits

The efficient implementation of adders in differential logic can be carried out using a new generate signal (N) presented in this paper. This signal enables iterative shared transistor structures to be built with a better speed/area performance than a conventional implementation. It also allows adders developed in domino logic to be easily adapted to differential logic. Based on this signal, three 32-b adders in differential cascode switch voltage (DCVS) logic with completion circuit for applications in self-timed circuits have been fabricated in a standard 1.0-μm two-level metal CMOS technology. The adders are: a ripple-carry (RC) adder, a carry look-ahead (CLA) adder, and a binary carry look-ahead (BCL) adder. The RC adder has the best levels of performance for random input data, but its delay is significantly influenced by the length of the carry propagation path, and thus is not recommended in circuits with nonrandom input operands. The BCL adder is the fastest but has a high cost in chip area. The CLA adder provides an intermediate option, with an area which is 20% greater than that of the RC adder. Its average delay is slightly greater than that of the other two adders, with an addition time which increases slowly with the carry propagate length even for adders with a high number of bits     

Shunt-feedback Schottky clamped logic gates

A new approach to digital circuit design is used to develop a new family of TTL-compatible shunt-feedback Schottky clamped logic gates. The virtual ground like input of the shunt-feedback amplifier and the low-impedance input of the familiar diode-biased current source are utilized to perform certain logic and fan-out operations without requiring full logic swings. Voting logic operations as well as conventional Boolean logic operations, such as AND, NAND, OR, NOR, AND-OR, AOI, etc., can all be performed with approximately the same one-gate delay of 2.5 ns. Average dissipation of the NAND gate is 17 mW. The series-terminated transmission-line connection without requiring full logic swing is described.     

Top-down pass-transistor logic design

The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with conventional cell based design. An extremely simple cell library with only seven cells combined with a synthesis tool called “circuit inventor” is compared with the conventional CMOS library that has over 60 cells combined with the state-of-the-art logic synthesis. The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three. This demonstrates that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost. Key issues which have to be cleared before pass transistor logic is used as the generic logic scheme replacing CMOS are also discussed     

0.8 V CMOS adiabatic differential switch logic circuit using bootstrap technique for low-voltage low-power VLSI

A novel 0.8 V CMOS adiabatic differential switch logic (ADSL) circuit using the bootstrap technique for low-voltage low-power VLSI is reported. Using capacitance coupling effects from the bootstrap transistors with the related isolating transistors, this 0.8 VADSL circuit has a 52% smaller propagation delay time, consuming 26% less power as compared to the energy efficient logic circuit.     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

Design and application of CMOS bulk input scheme

This work presents CMOS bulk input differential logic (BIDL) circuits. The bulk input scheme is applied to enable bulk terminals to receive signals. A boost circuit is employed to the bulk terminal of an input device. A multiple-input boost circuit is also developed to improve the flexibility of logic design. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to a low parasitic resistive and capacitive load. The BIDL has better speed and power performance than conventional differential logic circuits. The flexibility of the logic design is greatly improved. The BIDL is applied to a divide-by-128/129 frequency synthesizer using a 0.25-/spl mu/m CMOS process. Measurement results of the test chip indicate that the operating frequency is 2 GHz at a supply voltage of 2.5 V.     

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.     

A multi coding technique to reduce transition activity in VLSI circuits

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.     

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

Low-power logic styles: CMOS versus pass-transistor logic

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern     

Variable Input Delay CMOS Logic for Low Power Design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.     

On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V