用于高Gb／s光通信系统的新型时钟提取电路

新型时钟提取电路省去传统提取电路中的非线性处理电路，从而简化了接收设备。在利用这种电路的光通信系统中，在发送端，时钟脉冲叠加在数字信号上；在接收端，主放电路以后分成两个通路，一通路接有一个Ｎｙｑｕｉｓｔ滤波器，只允许信号脉冲通过，另一路则接有一窄带滤波器，实现时钟信号的提取。为了验证此方案的可实现性，研制出一套１．２４４Ｇｂ／ｓ光通信系统。本文从理论上分析这种光通信接收机的灵敏度与时钟脉冲调制度及时移的关系，并与实验结果相对比。另一方面，还建立了一个简单的公式计算所提取的时钟信号抖动值。     

基于FPGA的光纤通信系统中帧同步头检测设计

为实现设备中存在的低速数据光纤通信的同步复接／分接,提出一种基于FPGA的帧同步头信号提取检测方案,其中帧头由7位巴克码1110010组成,在数据的接收端首先从复接数据中提取时钟信号,进而检测帧同步信号,为数字分接提供起始信号,以实现数据的同步分接。买验表明,此方案成功地在光纤通信系统的接收端检测到帧同步信号,从而实现了数据的正确分接。     

Optical Clock Recovery Using a Polarization-Modulator-Based Frequency-Doubling Optoelectronic Oscillator

We propose and demonstrate a flexible optical clock recovery scheme using a polarization-modulator-based frequency-doubling optoelectronic oscillator (OEO). The proposed system can extract both prescaled clock and line-rate clock from a degraded high-speed digital signal using only low-frequency devices. A simple theory is developed to study the physical basis of the optical clock recovery. The OEO operation from a free-running mode to an injection-locking mode is investigated. The locking range is quantitatively predicted. An experiment is then implemented to verify the proposed scheme. A prescaled clock at 10 GHz and a line-rate clock at 20 GHz are successfully extracted from a degraded 20 Gb/s optical time-division-multiplexed (OTDM) signal. The locking range and the phase noise performance are also experimentally investigated. Clock recovery from data signals that have no explicit subharmonic tone is also achieved. The proposed system can be modified to extract prescaled clock and line-rate clock from 160 Gb/s data signal using all 40-GHz devices.      

All optical signal regularizing/regeneration using a nonlinearfiber Sagnac interferometer switch with signal-clock walk-off

All-optical signal regularizing/regeneration using a nonlinear fiber Sagnac interferometer switch (NSIS) that employs signal-clock walk-off is investigated. The NSIS realizes all-optical signal regeneration, including timing and amplitude regularizing, by switching clock pulses with amplified input signals using a walk-off-induced, wide, square switching window and intensity-dependent transmittance of the device. First, characteristics (in both the temporal and spectral domains) of the all-optical signal regeneration achieved with the NSIS are investigated theoretically and experimentally. They certify that if clock pulses are within the square switching window obtained with signal-clock walk-off, the clock pulses can be modulated according to the data that the input signals carry and retain their temporal and spectral profiles. This means that if clock pulses can be prepared that meet the system requirements, the NSIS can convert input signals that may not satisfy system requirements into high-quality output signals. Limitations on the switching contrast due to the cross-phase modulation of counterpropagating reference pulses is also discussed. Second, two possible applications of NSIS-based all-optical signal regularizing/regeneration, 1) an all-optical multiplexer with an optical clock and 2) an all-optical regenerative repeater, are discussed. Preliminary experiments with ~10-ps pulses at bit rates of ~5 Gb/s that use locally prepared optical clock pulses, show that the NSIS provides an error-free regeneration function with a certain tolerance for pulse-period irregularity if a proper optical clock is obtained     

Dynamically De-Skewable Clock Distribution Methodology

In a typical clock distribution scheme, a central clock signal is distributed to several sites on the integrated circuit (IC). Local regenerators at these sites buffer the clock signal for the logic in regions close to the regenerator. Minimizing the skew between the clocks at these regeneration sites is critical. In recent times, this is becoming harder due to increasing intra-die processing variations. In this paper, we describe a novel technique to distribute a clock signal from a central location to several sites on a VLSI IC. Our technique uses a buffered H-tree and includes circuitry to dynamically remove any skew that may result due to intra-die processing variations. While existing approaches to deskewing a clock tree have utilized several phase detection circuits (number of phase detectors dependent on the number of clock regenerators), our method requires only one phase detector. Also, in our approach, the resolution of the phase detector is inconsequential unlike existing techniques. Our deskewing technique can be applied dynamically, either at boot time or periodically during the operation of the IC. Using a six-level H-tree clock distribution network with process variations deliberately included, we demonstrate that our technique can reduce skews as high as 300 ps down to just 3 ps. We compare our clock tree with traditional buffered and unbuffered H-tree networks.      

基于JFM7K325T着陆设备时序信号设计与实现

针对飞机进场着陆问题，提出一种基于JFM7K325T着陆设备时序信号设计方案，JFM7K325T负责产生数字信号处理（DSP）的时钟、复位、逻辑控制和数据的预处理，在时钟的同步下按一定格式产生不同功能的着陆设备数据信号，并通过试验验证该方案的可行性。     

Timing Jitter Reduction by All-Optical Signal Regeneration Using a Polarization Bistable VCSEL

All-optical signal regeneration is experimentally demonstrated using a polarization bistable vertical-cavity surface-emitting laser. The retiming operation of signal regeneration is performed by using an AND gate operation and a reset operation. An optical clock pulse and input data signal are used for the AND gate operation. The timing jitter of the regenerated signal is reduced by optimizing the injection power ratio of the clock pulse and the data signal. The retiming operation is analyzed using a simple model that includes random fluctuation of the polarization switching threshold and bandwidth limitation of the response to the injection light.      

恶化非归零码信号的全光时钟恢复

全光时钟提取结构应对输入信号的恶化程度有一定的容忍度.在一种半导体光放大器(SOA) 啁啾光纤布拉格光栅(CFBG) 受激布里渊散射(SBS)的方式实现非归零(NRZ)码信号的全光时钟提取结构中,半导体光放大器和啁啾光纤布拉格光栅共同作用实现了非归零码信号的时钟分量增强,基于受激布里渊散射的全光时钟提取结构提取出非归零码的光时钟信号.实验通过对不同恶化程度的非归零码信号的时钟提取比较发现,恶化信号的信噪比是影响光时钟提取的关键.输入非归零码信号的信噪比越差,光时钟信号光谱的噪声水平越高,提取出的光时钟信号的幅度越低.当时钟增强非归零码信号的时钟数据抑制比低于-10 dB时,无法实现非归零码信号的时钟提取.     

Burst-Mode Clock Recovery Utilizing Relaxation Oscillation in Directly Modulated Lasers

A novel clock recovery scheme utilizing the relaxation oscillation in a directly modulated laser (DML) for burst-mode transmission is proposed for the first time. In this scheme, the DML generates the clock tone along with the transmitted non-return-to-zero data in the optical signal. An injection-locked oscillator (ILO) is employed in the receiver to extract the clock tone and restore the clock. The proposed scheme is investigated systematically and verified by simulations with different laser modulation currents as well as some nonideal characteristics of the system. The simulation results show that the low cost clock recovery method using an ILO in an optical link using a regular DML is highly efficient for burst-mode transmission at 10 Gbps.     

Time-transfer performance in burst-mode communication systems

This paper studies the performance of the clock transfer scheme for burst-mode communication systems for which data are received during short, equally spaced intervals. Its main focus is on satellite-based time-division multiple-access (TDMA) communication systems with data regeneration and switching onboard the satellite, although the results apply to other TDMA systems as well. The system reference clock is generated onboard from an incoming, very stable ground source, based on a burst-mode demodulator that extracts the clock from a discontinuous modulated carrier due to the bursty nature of TDMA signals. If good enough, this onboard regenerated clock avoids the use of bulky and expensive clocks in the satellite payload and can act as the master clock of the TDMA system     

Bit rate and wavelength transparent all-optical clock recovery scheme for NRZ-coded PRBS signals

All-optical clock recovery from 40-Gb/s nonreturn-to-zero (NRZ) pseudorandom binary sequence data streams based on self-pulsating lasers is presented. A compact preprocessing circuit is utilized to convert an NRZ signal to a pseudoreturn-to-zero sequence before injecting into the optical clock. It comprises a semiconductor optical amplifier followed by a periodical wavelength-division-multiplexing demultiplexer filter. A stable sinusoidal clock signal with a root-mean-square jitter below 700 fs is detected at the output of the self-pulsating laser within data dynamic range of more than 8 dB. The performance of the all-optical clock recovery scheme is investigated by varying the bit rates between 39.81 and 43.02 Gb/s as well as for various wavelengths in the C-band.     

40 Gbps All‐Optical 3R Regeneration and Format Conversion with Related InP‐Based Semiconductor Devices

We report an experimental demonstration of 40 Gbps all‐optical 3R regeneration with all‐optical clock recovery based on InP semiconductor devices. We also obtain all optical non‐return‐to‐zero to return‐to‐zero (NRZ‐to‐RZ) format conversion using the recovered clock signal at 10 Gbps and 40 Gbps. It leads to a good performance using a Mach‐Zehnder interferometric wavelength converter and a self‐pulsating laser diode (LD). The self‐pulsating LD serves a recovered clock, which has an rms timing jitter as low as sub‐picosecond. In the case of 3R regeneration of RZ data, we achieve a 1.0 dB power penalty at 10^?9 BER after demultiplexing 40 Gbps to 10 Gbps with an eletro‐absorption modulator. The regenerated 3R data shows stable error‐free operation with no BER floor for all channels. The combination of these functional devices provides all‐optical 3R regeneration with NRZ‐to‐RZ conversion.     

Delay-and-multiply clock regeneration in APD-based direct-detectionoptical OOK communication systems

A clock recovery scheme for direct-detection optical on-off keying (OOK) communication systems with nonreturn-to-zero pulse shaping is proposed and investigated. In the suggested model, the optical field is detected with the aid of an avalanche photodiode (APD) photodetector, which is followed by a clock regeneration subsystem. The proposed clock recovery subsystem consists of a delay-and-multiply nonlinearity followed by a conventional phase-locked loop (PLL), tuned to the slot frequency of the desired optical OOK signal. Performance of the proposed system is obtained in terms of the signal-to-noise ratio (SNR_L) of the linearized PLL device (or, equivalently, the inverse of phase, or timing, error variance) when background noise and receiver thermal noise are present. Numerical results are presented in order to explain the influence of noise processes on the performance of the proposed clock recovery subsystem. The performance of this system is also compared to that of an early-late gate and square-law symbol synchronizers     

Applications of single and dual gate GaAs MESFETs for Gbit/s optical data transfer systems

Intrinsic large signal rise and fall times of less than 30 ps without charge storage demonstrate the potential of single and dual gate GaAs MESFETs for Gbit/s optical communication systems. The applications as signal regenerator, bit synchronizer, laser modulator, multiplexer, and demultiplexer are shown. Using only one dual gate GaAs MESFET clock and pulse shape regeneration as well as 1 Gbit/s laser modulation is performed. Bit synchronization is demonstrated up to 4 Gbit/s. 1 to 2 Gbit/s and 2 to 4 Gbit/s multiplexing as well as 2 to 1 Gbit/s demultiplexing with additional clock and pulse shape regeneration is shown using dual gate FETs. 2 to 4 Gbit/s multiplexing without clock regeneration is also accomplished using single gate GaAs MESFETs.     

A new parallel link interface with current-mode incremental signaling and per-pin skew compensation

This paper proposes a new current-mode incremental signaling parallel link interface with per-pin skew compensation. Per-pin skew compensation is carried out in a calibration phase where clock-like training data are sent to all channels along with a reference clock of the same frequency. Training data are deskewed with respect to the common reference clock using DLLs such that all channels are skew-compensated simultaneously. New encoding and decoding scheme have been proposed to reduce the signal critical path at the transmitter. Transimpedance amplifiers with replica biasing are used to perform current-to-voltage conversion at the receiving end with a minimum sensitivity to supply voltage fluctuation. To evaluate the performance of the proposed skew compensating technique, a 1 Gbytes/s parallel link interface consisting of two data channels and one reference clock channel has been implemented with UMC 0.13 μm 1.2 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BIM3V3 device models. The channels are modeled as 50 Ω microstrip lines on a FR-4 substrate. Simulation results of the parallel link at all process corners have demonstrated that the proposed parallel link interface provides a minimum deskew range of 1.2 ns (±0.6 ns in each direction).     

A Single Chip 160 Mbit/s Cable Communication Circuit Including a Gain Controlled Equalizer and a Data Regenerating PFLL

In this paper a single chip transmitter and receiver interface circuit for 160 Mbit/s CMI-coded data transmission is presented. The receiver circuit includes a 12 dB cable equalizer to compensate for nonconstant cable attenuations. There is also a PFLL for data regeneration and to extract a 320 MHz oscillator clock signal. The frequency characteristics of the equalizer are controlled with an automatic gain control loop (AGC). The PFLL is a combination of two separate control loops, the purpose of which is to keep the integrated oscillator on the narrow locking range of the data loop. The frequency loop has been designed with a frequency detector to avoid interferences between the two control loops. The transmitter includes a cable driver supplying a stable 1 Vpp signal amplitude to the transmission line and also a PLL to extract a 320 MHz clock signal.     

High-Speed Optical Time-Division Multiple-Access (OTDMA) Networks Using Optical Signal Processing

In this paper, we design high-speed optical fiber networks based on the time-division multiple-access (TDMA) technique. To achieve an ultrahigh throughput, optical signal processing should be used in the network. We present a feasible scheme to implement optical TDMA networks, with the emphasis on optical clock distribution, synchronization, and optical time demultiplexing. Since the proposed network uses two wavelengths to carry optical TDMA and clock signals respectively, at each TDMA receiver slot synchronization is feasibly achieved by using simple optical delay lines to process the separated optical clock and TDMA signals. This in turn allows us to build a large-scale distribution network which is attractive for future HDTV broadcasting applications. Using the proposed scheme also allows to implement a high-capacity broadcast and select optical TDMA network for real-time data communications.     

Recovery of 80 GHz optical clock from 160 Gbit/s data using regeneratively modelocked laser diode

An 80 GHz optical clock signal was successfully recovered from a 160 Gbit/s data stream using a regeneratively modelocking scheme of a semiconductor modelocked laser (MLLD). To handle an 80 GHz electrical signal, the MLLD integrated with a high-mesa electroabsorption modulator and a W-band UTC-PD module are used in this scheme.     

采用两个级联外部调制器产生四倍频光载毫米波的光纤无线通信系统

研究了一种采用两个级联外部调制器基于光载波抑制原理产生四倍频毫米波的光纤无线通信(ROF)系统.在中心站利用电混频器产生副载波复用信号,通过第一个外部调制器产生两倍射频(RF)信号的光载毫米波信号,再通过第二个外部调制器产生四倍射频信号的光载毫米波.实验显示采用频率为10 GHz的射频信号源和2.5 Gbit/s的数据基带信号混频通过两个级联外部凋制器后产生毫米波的频率为40 GHz,并且在单模光纤中传输距离达20 km,功率代价小于2 dB.     

RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time