A novel ternary logic circuit using Josephson junction

A novel Josephson complementary ternary logic (JCTL) circuit is described. This fundamental circuit is based on the combination of two SQUIDs (superconducting quantum interference devices), one of which is switched in the positive direction and the other in the negative direction. The JCTL can perform the fundamental operations of AND, OR, NOT, and Double NOT in ternary form. The principle of the operation and design criteria are described in detail. Simulation results show that reliable operation of these circuits can be achieved with a high performance     

1988 Applied Superconductivity Conference

The following topics are dealt with: superconducting electronics; superconducting quantum interference devices (SQUIDs); magnetometers; Josephson device memories; thin-film superconducting materials; tunnel junctions; Josephson device logic circuits; high-T_c (critical temperature) superconductors; YBaCuO superconductors: ceramic superconductor memories; millimeter-wave detectors; Josephson device mixers; superconducting transmission-line structure; superconducting microwave cavities; tunnel spectroscopy; laser-induced switching of superconductors; gradiometers; harmonic mixing; SIS (superconductor-insulator-superconductor) mixers; superconducting bolometers; superconductor device fabrication; SSC; (Superconductor Super Collider); magnets; superconducting magnets; chaos in Josephson junction systems; superconducting coils; superconducting material preparation; MHD; (magnetohydrodynamics) magnets; magnetic resonance imaging (MRI) magnets; and niobium materials devices     

RSFQ logic arithmetic

Several ways to achieve local timing of Josephson-junction RSFQ (rapid single flux quantum) logic elements are proposed. Several examples of serial and parallel pipelined arithmetic blocks using various types of timing are suggested and their possible performance is discussed. Serial devices enable one to perform n-bit functions relatively slowly but using integrated circuits of a moderate integration scale, while parallel pipelined devices are more hardware-wasteful but promise extremely high productivity. The possible local and self-timing of RSFQ logic elements has been demonstrated, making it possible to construct digital blocks and complex devices operating at extremely high clock frequencies, limited only by logic delays of the RSFQ elements (~100 GHz for the present-day Nb technologies)     

New complementary logic circuits using coupled open quantum systems

This paper present new complementary logic circuits that exploit an intrinsic bistability in nanoscale coupled open quantum systems such as wells and wires. When operated with a multiple-phase split-level clocking scheme, the device can latch a binary digit while meeting gain, tolerance, and I/O decoupling requirements at the same time, which was difficult with conventional back-to-back negative differential resistance devices. This same structure in a dual-rail configuration can function as a complete set of classical logic circuits by changing only the connections of the input signals. When these circuits are combined to form a sequential circuit, low power operation is expected, thanks to better voltage scaling, a zero-standby-power equalized state, and efficient charge recycling.     

Chiro-Optoelectronic Encodable Multilevel Thin Film Electronic Elements with Active Bio-Organic Electrolyte Layer

It is suggested that chiral photonic bio-enabled integrated thin-film electronic elements can pave the base for next-generation optoelectronic processing, including quantum coding for encryption as well as integrated multi-level logic circuits. Despite recent advances, thin-film electronics for encryption applications with large-scale reconfigurable and multi-valued logic systems are not reported to date. Herein, highly secure optoelectronic encryption logic elements are demonstrated by facilitating the humidity-sensitive helicoidal organization of chiral nematic phases of cellulose nanocrystals (CNCs) as an active electrolyte layer combined with printed organic semiconducting channels. The ionic-strength controlled tunable photonic band gap facilitates distinguishable and quantized 13-bit electric signals triggered by repetitive changes of humidity, voltage, and the polarization state of the incident light. As a proof-of-concept, the integrated circuits responding to circularly polarized light and humidity are demonstrated as unique physically unclonable functional devices with high-level logic rarely achieved. The convergence between functional nanomaterials and the multi-valued logic thin-film electronic elements can provide optoelectronic counterfeiting, imaging, and information processing with multilevel logic nodes.     

An Extended Approach for Generating Unitary Matrices for Quantum Circuits

In this paper, we do research on generating unitary matrices for quantum circuits automatically. We consider that quantum circuits are divided into six types, and the unitary operator expressions for each type are offered. Based on this, we propose an algorithm for computing the circuit unitary matrices in detail. Then, for quantum logic circuits composed of quantum logic gates, a faster method to compute unitary matrices of quantum circuits with truth table is introduced as a supplement. Finally, we apply the proposed algorithm to different reversible benchmark circuits based on NCT library (including NOT gate, Controlled-NOT gate, Toffoli gate) and generalized Toffoli (GT) library and provide our experimental results.     

Noise-tolerant quantum MOS circuits using resonant tunneling devices

Resonant tunneling devices are promising candidates for comingling with traditional CMOS circuits, yielding better performance in terms of reduced silicon area, faster circuit speeds, lower power consumption, and improved circuit noise margin. These resonant tunneling devices have several intrinsic merits that include: high current density, low intrinsic capacitance, the negative differential resistance effect, and relative ease of fabrication. In this paper, we briefly describe some circuit configurations of Silicon quantum MOS logic family, with a special emphasis on noise-tolerant design that is now becoming an important constraint for robust and reliable operation of very deep submicron VLSI chips. More specifically, we discuss a novel strategy to incorporate quantum-tunneling devices into mainstream dynamic CMOS circuits with a view to improving the noise immunity of the latter. Dynamic CMOS circuits are rampantly used in modern high-performance VLSI chips achieving the best tradeoff between circuit speed, silicon area, and power consumption. However, they are inherently less noise-tolerant than their static CMOS counterparts. With the continuously deteriorating noise margins due to aggressive down scaling of the CMOS fabrication technologies, the performance overhead due to existing remedial noise-tolerant circuit techniques becomes prohibitively high. In this paper, we propose a novel method that utilizes the negative differential resistance property of quantum tunneling devices. The performance and noise immunity of the proposed circuits are evaluated through both analytical studies and SPICE simulations. We demonstrate that the noise tolerance of dynamic CMOS circuits can be greatly improved with very little degradation in circuit speed. The benefit of the proposed technique is evident even for currently available Silicon-based resonant tunneling devices with a relatively small peak-to-valley current ratio.     

High-speed Josephson integrated circuit technology

The author describes recent progress in high-speed integrated circuits using niobium junctions. He briefly describes the circuit fabrication process and then introduces the modified variable threshold logic (MVTL) gate family. The lowest experimentally obtained MVTL OR-gate delay was only 2.5 ps with a power consumption of 17 μW/gate. This gate family is used in various high-speed logic circuits, such as 8-bit shift registers, 16-bit ALUs (arithmetic logic units), and 4-bit microprocessors. The author confirmed the high-speed operation of less than 10 ps per gate on average for these circuits. A novel high-sensitivity magnetic sensor using a SQUID (superconducting quantum interference device) was also developed. It is called a single-chip SQUID magnetometer because the feedback circuit, which is operated at room temperature is a conventional SQUID system, has been integrated on the same chip as the SQUID sensor itself     

Quantum computing based on a superconducting quantum interference device: exploiting the flux basis

Two classes of superconducting devices have been proposed as quantum bits (qubits) for realizing quantum logic operations. The flux qubits based on a superconducting quantum interference device (SQUID) appear to be particularly promising owing to the macroscopic nature of the qubit and potential integration with high-speed control circuitry in the form of rapid single-flux quantum electronics. Recent progress is discussed and near-term challenges mentioned. The radio frequency SQUID-based qubit offers a prospect for a reliably manufacturable scalable approach.     

Aspects of Qubit Dynamics in the Presence of Leakage

Nano-electronics devices such as small-capacitance Josephsonjunction circuits appear to be promising systems to implementquantum logic. While the elementary unit of a quantum computeris a two-state system (the qubit) the computational space of aJosephson junction qubit is a subset of a larger Hilbertspace. Therefore quantum leakage may occur, i.e. during theoperation of the device the quantum state may escape partiallyfrom the computational subspace. We study the consequences ofleakage for the fidelity of Josephson qubits and discuss howthe gate design can be optimized.     

Coherent Caloritronics in Josephson-Based Nanocircuits

We describe here the first experimental realization of a heat interferometer, thermal counterpart of the well-known superconducting quantum interference device. These findings demonstrate, in the first place, the existence of phase-dependent heat transport in Josephson-based superconducting circuits and, in the second place, open the way to novel ways of mastering heat at the nanoscale. Combining the use of external magnetic fields for phase biasing and different Josephson junction architectures we show here that a number of heat interference patterns can be obtained. The experimental realization of these architectures, besides being relevant from a fundamental physics point of view, might find important technological application as building blocks of phase-coherent quantum thermal circuits. In particular, the performance of two different heat rectifying devices is analyzed.     

Quantum Algorithms and Experiment Implementations Based on IBM Q

With the rapid development of quantum theory and technology in recent years, especially the emergence of some quantum cloud computing platforms, more and more researchers are not satisfied with the theoretical derivation and simulation verification of quantum computation (especially quantum algorithms), experimental verification on real quantum devices has become a new trend. In this paper, three representative quantum algorithms, namely Deutsch-Jozsa, Grover, and Shor algorithms, are briefly depicted, and then their implementation circuits are presented, respectively. We program these circuits on python with QISKit to connect the remote real quantum devices (i.e., ibmqx4, ibmqx5) on IBM Q to verify these algorithms. The experimental results not only show the feasibility of these algorithms, but also serve to evaluate the functionality of these devices.     

Nanowire spintronics for storage class memories and logic

Patterned magnetic nanowires are extremely well suited for data storage and logic devices. They offer non-volatile storage, fast switching times, efficient operation and a bistable magnetic configuration that are convenient for representing digital information. Key to this is the high level of control that is possible over the position and behaviour of domain walls (DWs) in magnetic nanowires. Magnetic random access memory based on the propagation of DWs in nanowires has been released commercially, while more dynamic shift register memory and logic circuits have been demonstrated. Here, we discuss the present standing of this technology as well as reviewing some of the basic DW effects that have been observed and the underlying physics of DW motion. We also discuss the future direction of magnetic nanowire technology to look at possible developments, hurdles to overcome and what nanowire devices may appear in the future, both in classical information technology and beyond into quantum computation and biology.     

Modeling Multiterminal Spintronic Devices

We are encountering tremendous opportunities and challenges in combining emerging nanotechnology for developing nanoelectronic devices. Researchers are designing nanoelectronic circuits based on newly discovered nanoscale building blocks, such as spintronic devices. In this paper, we calculate conductance in spintronic gates using the nonequilibrium Green's function and show useful operations for "multiterminal" logic gates. These spintronic devices can be used to design complicated spin circuits     

Simulation of a NDRO memory cell with very small excess current Josephson junctions

The dynamic behaviour of a single flux quantum NDRO interferometer cell with two very small excess current Josephson junctions is simulated for a clamping impedance parallel to the interferometer inductance. A proper design of the clamping impedance yields the required NDRO and written operations at large damping parameters β > 1000 of the Josephson junctions. Since large damping parameters are required for logic circuits the proposed NDRO memory cell and logic circuits can now be implemented with the same fabrication process.     

Magnetic bubble logic

Although the literature on the bubble logic devices is limited, the concepts and device configurations are diverse. In conductor-access devices, logic can be performed by bubble transfer operations. In field-access devices, logic can be performed by providing alternative paths which are selected by interaction between bubbles. Examples include the conjugate logic gates, the resident-bubble cellular logic, and the chevron 3-3 circuits. Logic can also be performed by counting bubbles, such as in the symmetric switching function implementation. The various mechanisms for implementing bubble logic are all described by truth tables. To assess their efficiency, they are compared in terms of space and delay when they are used to implement the same logic element - a full adder. They are all comparable except for the resident-bubble cellular logic which requires excessive space and delay. However, it is important to point out that only the symmetric switching function devices offer rewrite-ability to eliminate the part number problem, and accommodation for a large number of inputs to ease interconnection and delay equalization problems.     

Arithmetic logic unit of a computer based on spin-polarised single electrons

The design of an arithmetic logic unit (ALU) is presented using 'single spin logic' where classical binary bits 0 and 1 are encoded in orthogonal spin polarisations of single electrons hosted in semiconductor quantum dots. The logic signal (spin state) is transmitted from one spin to the next via nearest-neighbour exchange interaction. The ALU circuits are implemented by placing the quantum dots in specific geometric patterns on a wafer so as to realise the desired relationships between the input and output spin states.     

Speed-limiting factors in flash-type Josephson A/D converters

The authors discuss the causes of speed limitations in various A/D (analog/digital) converter designs. The upper limit on bandwidth is extracted with the help of Josephson SPICE simulations. In the Josephson A/D converter circuits discussed, the dynamic properties of the SQUIDs (superconducting quantum interference devices) determine the aperture time and dictate the bandwidth. Designs for 4-bit A/D converters that show potential for bandwidths on the order of 10 GHz are described. Particular attention is given to the bit-parallel A/D converter with self-gating AND comparator and bit-parallel A/D converters with CLAM (current latching analog microcomparator) and variable-pulse peak comparators     

通用逻辑门电路的SET实现及应用

通用逻辑门具有更强的逻辑功能,相比传统逻辑门更适合作为阵列逻辑单元。单电子晶体管（SingleElectronTransistor,SET）被认为是众多纳米电子器件中的强有力竞争者。为了拓展SET的应用,减少逻辑综合所用逻辑门的种类,提出了通用逻辑门的SET电路实现方案,设计出基于sET的通用逻辑门树形结构的全比较器等电路,用Hspicer软件对所设计的电路进行仿真,结果表明,该电路具有正确的逻辑功能,为SET通用逻辑门的进一步研究应用奠定了基础。     

Gallium arsenide digital integrated circuits

The motivations behind the development of GaAs integrated circuits (IC) are two-fold: to integrate high speed logic with optical sources and to meet the increasing demand of realising LSI/VLSI with higher speed and lower power dissipation for large scale computer applications. GaAs gigabit circuits have been growing in complexity to more than 3000 gates on a single chip. Although this is encouraging, more efforts are needed to improve production yield. By far the most work on GaAs digital IC has been done using MESFET as the active devices. MOSFET technology is yet to mature from the practical IC point of view. The logic gate types used in circuits are predominantly of the enhancement-mode driver and depletion-mode load configuration (E/D). A brief survey of the state-of-the-art of GaAs digital IC is presented. Implemented circuits are described and compared with those achieved through various technologies. GaAs gate arrays, multipliers, accumulators and memories are discussed. At liquid N₂-temperature, a switching time of 5·8 ps/gate has been achieved for 0·35μm gate devices. This and similar other results lead to the conclusion that at the VLSI level of future Gbit circuits, GaAs devices in the form of HEMT operated at 77 K can outperform Si-devices. At′ LSI complexities, experimental GaAs MESFET and 300 K HEMT have a lead on Sicircuits—it is then this range in which Gbit/GaAs should find their application.