利用常系数乘法器设计高效FIR滤波器

介绍了一种用常系数乘法器 (KCM )来设计FIR滤波器的方法。详细阐述了FIR滤波器的结构、设计过程及其用KCM设计方法的优越性     

基于高速流水线乘加器的FIR滤波器设计

本文介绍了一种有限冲击响应(FIR)滤波器的设计,其核心部分采用12×12位流水线乘加单元(MAC)实现。乘加结构中采用非重叠多位编码产生部分积,结合进位保留加法(CSA)阵列,通过超前进位加法器(CLA)累加产生最终结果。采用VHDL对FIR滤波器进行了描述,并在FPGA中进行了综合验证。     

FIR滤波器的设计

数字滤波器现正日益广泛地应用在通信、音响、图象等领域之中。数字滤波器有“无限冲激响应型(IIR型)”和“有限冲激响应型(FIR型)”之分。本文讲解FIR滤波器的设计问题,较全面地介绍了它的各种优化设计方法,如傅里叶级数展开法、窗函数法、Remez Exchange法、预滤波器-均衡器构成法、内插法等。文章以初、中级技术人员为对象,给出了设计步骤、设计实例和一部分设计程序。     

应用分布式算法在FPGA平台实现FIR低通滤波器

在利用FPGA实现数字信号处理方面,分布式算法发挥着关键作用,与传统的乘加结构相比,具有并行处理的高效性特点。本文研究了一种16阶FIR滤波器的FPGA设计方法,采用VerilogHDL语言描述设计文件,在XilinxISE7.1i及ModelSimSE6.1b平台上进行了实验仿真及时序分析,并探讨了实际工程中硬件资源利用率及运算速度等问题。     

基于FPGA的FIR滤波器设计

数字信号处理技术广泛应用于各种工程技术领域,而数字滤波器在数字信号处理过程中起到很重要的作用,本文通过对原理和结构的分析,结合了Matlab软件和QuartusII软件介绍了一种线性相位的15阶的FIR数字滤波器的设计方法,并且通过软件的仿真功能,验证了设计的FIR滤波器的可行性以及正确性。     

基于遗传算法的FIR可变分数延迟滤波器设计

分数延迟滤波器广泛用于语音处理,回声消除,多速率信号处理等方面.文中设计的FIR可变分数延迟滤波器用于解决全数字接收机的时钟同步问题.首先用传统的加权最小平方误差方法设计出滤波器参数,然后通过遗传算法对参数进行优化并通过matlab仿真验证算法的有效性,仿真结果表明所设计的滤波器有很好的幅度特性和相位延迟特性.     

多波束回波信号可变带宽滤波算法及其FPGA实现

噪声是限制多波束测深声呐深度估计精度的重要因素,目前在声呐系统中广泛采用的噪声抑制方法是固定带宽滤波。针对测量扇面内不同方向上噪声影响程度不同的特点,该文提出一种新的可变带宽滤波算法并依据多波束回波特性设计了相应的滤波器,与传统滤波方法相比,可以有效地提高信噪比,并且运算量小;其滤波算法结构非常有利于 FPGA的快速实现。文中给出了该滤波算法的FPGA实现结构,并仿真验证了该滤波算法的工程可行性。对湖上试验数据的处理结果验证了该算法的有效性。     

基于DSP的FIR低通滤波器设计

介绍了FIR滤波器的基本结构和设计方法。根据要求,借助MATLAB辅助工具采用窗函数方法对滤波器的系统函数进行设计。利用设置循环缓冲区的方法对数据进行存储,通过DSP汇编语言编程,结合TMS320C5402为核心的实验平台实现了FIR低通滤波器的设计。实验结果表明,该设计精度高、稳定性好,操作方便,有一定的实用价值。     

基于FM接收机的可变带宽频率综合器设计

本文介绍了应用在单芯片FM接收系统中可变带宽频率综合器的设计.通过同时改变电荷泵电流和滤波器的结构使锁相环的带宽发生变化,这样在不影响噪声性能(phase jitter)的前提下,锁定时间显著减小.在大电流状态下,环路带宽比锁定状态下提高了4.6倍.电路设计是采用0.6μm BICMOS工艺,仿真结果显示,在3V的电源电压下,锁定时VCO纹波电压小于0.2mV,功耗大约12mW.     

数字滤波器(FIR)设计算法研究

FIR数字滤波器具有线性相位、稳定性好等特点,被广泛地应用于生产实践中。关于FIR数字滤波器设计的算法很多,线性规划法和外插法就是其中两种。分别对该两种算法建立相关模型并通过MATLAB进行仿真,结果表明线性规划法得到的设计结果性能较好,但是变量数相对较多,复杂度较大。而外插法则是基于线性规划法的改进算法,该算法权衡了复杂度与性能,使其更适合于工程实际运用。     

A Survey of FIR Filter Design Techniques: Low-complexity,Narrow Transition-band and Variable Bandwidth

In the present century, digital signal processing (DSP) approaches are considered to be one of the most powerful technologies which may shape the science and technology in coming decades. From 1970 onwards, a drastic revolution took place in a wider domain of DSP which has made it popular in several studies such as radar and sonar signal processing, digital televisions, wireless communication scenarios and other multimedia setup etc. Digital filters form the backbone of this DSP architecture and in point of fact the field of digital filter design has drawn justified recognition from the researchers throughout the world for the last 50 years. In connection to this, thousands of research articles may be found from the literature which had extensively addressed on the design of such filters. In order to meet the requirement of narrow transition-band, finite impulse response (FIR) filters are commonly assumed to be of higher order and accordingly it significantly enhances computational complexity. In regard to this, construction of hardware efficient digital filters had drawn significant consideration which aims to include minimum hardware elements during its application and consequently consumes less power. This review paper illustrates various techniques for the implementation of hardware efficient narrow transition-band FIR filter and investigates a number of favourable attributes which are capable in sustaining the stringent requirements of communication standards. A good number of relevant articles are taken from the literature so as to make a robust and complete review.     

二维线性相位FIR滤波器设计的投影最小二乘算法

考虑二维线性相位矩形对称FIR滤波器的约束最小二乘设计问题,即在通带和阻带逼近误差不超过给定值的约束下使逼近误差平方和最小.提出一个投影最小二乘算法,它是一个交替地更新有效约束集及将二次误差无约束极小点(最小二乘解)逐次投影到有效约束边界的迭代过程.通过二维FIR低通圆形滤波器和方形滤波器的设计例子,对算法的性能进行了仿真,并与基于内点算法和有效集方法的设计程序进行了比较,结果表明本文算法具有很高的效率.     

基于人工蜂群算法的FIR滤波器设计

FIR滤波器设计是数字信号处理领域中的重要课题之一。最优化FIR滤波器设计可以抽象为一个最优化问题,采用启发式算法来求解。作为一种新型启发式算法,人工蜂群算法由于其原理简单、控制参数少、鲁棒性强等优点,已被越来越多的学者所关注。本文采用人工蜂群算法优化FIR滤波器设计,研究了两者的结合机理,讨论了具体实现步骤,并通过仿真验证了该方法的有效性。     

Optimal Design of FIR Digital Filter Using Genetic Algorithm

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A New Low Latency Parallel FIR Filter Scheme

A new array type parallel scheme for an FIR digital filter is presented in this paper. The proposed scheme is based on the structure of the carry-save array multiplier where each cell implements the computation of an FIR filter at the bit-level. This structure leads to latency independent of the number of the filter taps. The proposed scheme is pipelined at the bit-level, is systolic at the cell-level and requires less hardware than other schemes based on discrete multipliers.Paraskevas Kalivas received his Diploma and Ph.D. degree in electrical and computer engineering from the National Technical University of Athens, Greece, in 1990 and 2000 respectively.His research interests include computer arithmetic and efficient realization of arithmetic circuits and digital filters.Vassilis Vassilakis received his Diploma in electrical and computer engineering from NationalTechnical University of Athens, Greece, in 1997. He isworking toward the Ph.D. degree in electrical engineering at National Technical University of Athens.His research interests include efficient circuit implemenation of DSP algorithms and java processor architectures.Chris Meletis received his Diploma in electrical and computer engineering from National Technical University of Athens in 1997. Currently, he is working toward the Ph.D. degree in electrical engineering at National Technical University of Athens.His research interests include multirate filter banks, digital filter design and their efficient realization.Kiamal Z. Pekmestzi received his Diploma in electrical engineering from the National Technical University of Athens, Greece, in 1975. From 1975 to 1981, he was a research fellow in the Electronics Department of the Nuclear Research Center Demokritos. He received his Ph.D. in electrical engineering from the University of Patras, Greece, in 1981.From 1983 to 1985, he was a professor at the Higher School of Electronics in Athens. Since 1985, he has been with the National Technical University of Athens, where he is currently a professor. His research interests include computer arithmetic, VLSI digital filters and VLSI design automation.     

一种低复杂度的稀疏FIR陷波滤波器的设计方法

FIR陷波滤波器具有线性相位、精度高、稳定性好等诸多优势,然而当陷波性能要求较高时,通常需要较高的阶数,导致FIR陷波滤波器硬件实现复杂度大大提高。该文基于稀疏FIR滤波器设计算法和共同子式消除的思想,提出一种低复杂度的FIR陷波滤波器设计方法。该方法首先采用稀疏滤波器设计算法得到满足频域性能设计要求的FIR陷波原始滤波器系数,然后对其进行CSD编码,并分析CSD编码量化系数集中所有的2项子式和孤子的灵敏度,最后根据灵敏度的大小依次选择合理的2项子式或孤子直接合成滤波器系数集。仿真结果表明,新算法设计实现的FIR陷波滤波器比已有的低复杂度设计方法最多可减少51%的加法器,有效地降低了硬件实现复杂度,大大节省了硬件资源。

     

基于Hanning Window设计FIR数字高通滤波器

基于实序列的傅里叶变换具有的特征,提出了一种研究线性相位FIR数字滤波器幅度函数的简洁方法。首先揭示了偶对称和奇对称的线性相位FIR数字滤波器幅度函数的特点;然后研究了矩形窗函数对线性相位理想数字低通滤波器幅频特性的影响,即时域加矩形窗,频域形成过渡带;最后介绍了利用窗函数法设计FIR数字滤波器时,对窗函数的要求,选择窗函数的依据及利用窗函数法设计FIR数字滤波器的步骤,并给出了基于Hanning Window来设计FIR数字高通滤波器的实例。     

基于雷米兹交换算法设计线性相位对数FIR滤波器

根据线性相位对数FIR滤波器幅度响应与线性相位FIR滤波器幅度响应的关系 ,将线性相位对数滤波器设计转换为线性相位FIR滤波器设计。该方法直接采用雷米兹交换算法即可获得线性相位对数滤波器通带和阻带的等纹波特性。另外 ,该方法既可基于频域均匀采样也可基于频域非均匀采样 ,具有一定的通用性和灵活性     

一种设计对数FIR数字滤波器的方法

本文提出了一种设计具有等波纹对数幅度响应的线性相位ＦＩＲ数字滤波器的方法,该设计方法以多次交换算法为基础。在给定通带与阻带误差比、通带误差和阻带误差三种情况下讨论该设计方法。介绍几个低通对数ＦＩＲ滤波器的设计例子,来说明该设计方法的效率。     

基于模块局部可重构FIR滤波器设计

介绍了一种使用动态局部重构技术设计可重构FIR数字滤波器的方法,是一种注重面积效率高、灵活性强,允许动态插入或删除局部模块的方法,并在Xilinx Virtex-4 FPGA上实现.这种设计方法比传统的FIR滤波器的设计方法具有占用资源更少、重构时间更短、高速灵活性等优点.