共查询到18条相似文献,搜索用时 109 毫秒
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一种嵌入式系统集成调试器的实现 总被引:2,自引:1,他引:1
主要给出了一种嵌入式系统集成调试器的具体实现方案,该嵌入式系统集成调试器以USB作为目标系统与PC机的接口,通过一个通用的PC端调试程序对目标板上的嵌入式处理器进行调试。在分析了2种嵌入式系统调试手段的同时,给出了一种新的嵌入系统调试方案,并给出了典型目标系统的硬件结构和调试软件结构。介绍了基于标准可执行文件解析的代码关联技术在调试软件中的应用。 相似文献
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CK·CORE嵌入式CPU调试器设计 总被引:1,自引:1,他引:0
调试嵌入式系统的软件是在系统开发中最为耗时的工作,软件占的比例也逐渐增加,已逐渐成为嵌入式系统产品上市时间重要因素,功能强大的调试器能缩短上市时间,保证开发产品质量。本文提出了一种基于片上仿真方式的调试器,为避免扫描链方法的问题,采用映像寄存器方式实现,增加了灵活性和可移植性,采用了一种远程代理结构,对自主知识产权的32位高性能嵌入式芯片CK·CORE的设计进行调试,并给出了与其它调试方式相比较的实验结果。 相似文献
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基于ARM&Linux的嵌入式设备远程调试模块设计 总被引:3,自引:1,他引:2
提供一种方便、高效的设备调试方案,即利用嵌入式技术采用网口替代常用的串行接口、USB接口等作为设备的调试接口.该系统以Atmel公司的AT91RM9200芯片为核心,以可裁减的μCLinux为操作系统,设计了嵌入式Web服务器.以此服务器为基础结合CGI技术实现设备远程调试器.给出系统硬件结构,介绍了Boa的移植和配置,并探讨了动态网页的设计方法.经实验,该系统具备高速、易用、传输距离远和无需上位机软件等优点;为设备调试和测控系统提供了一种有效的方案.这里利用嵌入式技术结合网络技术实现新型设备调试方案,比现有方案更灵活、高效、易用. 相似文献
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3.高级语言交互式调试器(C-SPY)⑴高级语言交互式调试器(C-SPY)的工作模式和启动高级语言交互式调试器(C-SPY)的工作方式有三种:①模拟方式(Simulation)。在这种方式下,目标系统的工作过程由调试主机以软件模拟的方式来实现,用户可以通过各种不同的窗口来观察调试程序的运行过程,即在目标硬件系统产生之前,验证程序的设计思想和程序结构。②仿真方式(Emulation)。在这种方式下,目标硬件系统通过JTAG接口与调试主机连接起来,使整个调试过程在目标硬件系统的真实运行下进行,不仅可以验证程序的设计思想和程序结构,还可以实际判断目标… 相似文献
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交叉调试是嵌入式系统开发的基本方式。基于采用PowerPC755处理器的调试目标机,设计并实现了基于Eclipse平台的集成开发环境MRTOS。该开发环境以Eclipse为调试前端,实现了与通用交叉调试器GDB的无缝集成,可实现对PowerPC755上目标程序的源代码级调试。 相似文献
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嵌入式发展需要新的调试工具 总被引:3,自引:0,他引:3
传统调试在嵌入式的发展过程中,当前的设计中使用32bit芯片的设计人员比过去大约多50%,大部分多处理器设计至少使用两种类型的处理器芯片,设计师们正开始从老的语言转向C++。增加着的软件/系统复杂性需要使用辅助硬件连接到目标系统的调试器上。有3种把... 相似文献
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Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time‐consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on‐chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run‐stop mode debugging. Compared with the debug architecture that supports the run‐stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on‐chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor. 相似文献
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Because of the intrinsic lack of internal‐system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on‐chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run‐stop‐type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG‐based scanning operation. We apply this on‐chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach. 相似文献
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Harald Vranken 《Journal of Electronic Testing》2000,16(3):301-308
This paper describes debug facilities in the Philips TriMedia CPU64, which is an embedded processor core for multimedia applications. Its architecture provides a VLIW pipeline, support for 64-bit vector data, and virtual memory management. The debug hardware in the TriMedia CPU64 supports two complementary debug strategies. One strategy provides a snapshot of the processor state at certain moments in time, which is achieved by single-step execution and various breakpoint types. The other debug strategy provides continuous monitoring of the processor state by using a PC trace buffer. Precise exceptions are used to provide accurate context switching from application software to debugger software. 相似文献
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用Indy组件设计通用网络调试器 总被引:2,自引:0,他引:2
网络通讯广泛应用于控制系统中,由于网络设备价格低廉,网络编程功能强大而备受推崇。越来越多的控制项目使用网络通讯实现,网络调试器是专为调试这类应用而设计的,他可以仿真通讯双方所有可能的情况,特别在航天测控项目中,中心机与许多其他设备分机互传信息时,常采用组播形式。这类应用程序调试较麻烦,有了通用网络调试器,程序员即可在很短时间内调试出自己的控制系统。该调试器可仿真任一理论弹道,动态给控制应用程序发送该理论弹道,为快速开发出这类应用程序提供强有力的支持。 相似文献