基于数值计算模型的MMC半桥型子模块仿真方法

模块化多电平换流器（MMC）的各半桥子模块均由两个开关组（1个IGBT和1个反并联的二极管）构成。针对MMC在包含的子模块规模较大的情况下,对采用电路模型分割法对MMC进行分割后的子模块进行仿真求解时仍然会占用较多资源,效率不高的问题,提出了基于数值计算模型的MMC半桥子模块仿真验证方法。首先通过分析三相MMC及其半桥子模块（HBSM）的工作机制,把半桥型子模块中的两个开关组等效为在高、低阻态不断切换的等效电阻并给出了其等效电路。然后针对电容支路的离散化问题,根据梯形积分法推导了MMC半桥型子模块的数值求解公式,给出了数值计算电路模型。最后基于MATLAB仿真平台建立了基于数值计算模型的半桥子模块仿真验证模型,通过与详细模型子模块的仿真波形对比分析,结果表明了所建立的子模块数值计算模型是可行的。     

混合式MMC直流故障穿越特性影响因素研究

混合式MMC利用全桥子模块的负压特性实现直流故障不闭锁穿越,由于直流故障穿越特性是考核换流阀设备与控制保护系统性能的重要指标,因此首先对混合式MMC直流故障穿越特性影响因素及其影响机理进行理论分析,主要包含控制器参数以及子模块配比两方面因素,然后搭建PSCAD系统仿真模型对其影响结果进行仿真验证并给出故障特性优化方法。结果表明,通过优化控制器参数可有效降低换流阀电气应力并缩短故障电流清除时间;故障期间在负投入子模块个数饱和的情况下,通过提升全桥子模块配比可缩短故障电流清除时间。     

MMC-HVDC直流双极短路故障电流分析

直流母线上双极短路故障是柔性直流输电系统最为严重的故障.目前针对模块化多电平换流器的高压直流输电(MMC-HVDC,modular multilevel converter based HVDC)系统故障的研究大多数侧重于故障的保护,而对于故障电流特性的研究只是简单的仿真分析.因此为了能够准确分析系统直流侧暂态故障电流的特性,通过对短路故障的暂态特性建立数学模型,进而分析MMC-HVDC系统直流母线上双极短路故障的暂态特性,推导出故障电流的数学表达式,并提出利用比例因子的方法来改进等效电容值,从而使故障电流计算值更精确.在PSCAD/EMTDC中搭建双端MMC-HVDC系统,对实验仿真波形与计算波形进行比较和分析,验证了所提方法的可行性与精确性.     

地铁牵引供电系统直流侧短路故障研究

牵引网短路故障中线路电气参数的暂态变化是研究轨道线路保护与控制技术和短路故障定位技术的基础。基于Matlab/Simulink建立了24脉波整流电路模型,计算了集肤效应作用下等效接触网与钢轨网的电阻和电感值,建立了直流牵引供电系统牵引网短路故障仿真模型,利用该模型对空载线路下牵引变电所近端与远端的牵引网短路故障进行仿真,分析电流瞬态值随不同故障距离变化情况。仿真结果曲线充分反应整流机组等非线性器件使得近端短路瞬态电流峰值呈振荡收敛状态,证明了该模型的准确性,为牵引变电系统线路保护装置的精确配置提供参考。     

一种新型直流故障限流器拓扑

基于模块化多电平换流器的高压直流输电技术迅速发展,直流侧短路故障电流的限制与开断困难等问题已然成为研究热点。故障限流技术能够快速的限制短路电流的峰值与上升率,为直流断路器的快速隔离提供有利条件。该文提出一种新型直流故障限流拓扑,通过在故障过程中降低等效电感、快速投入吸能电阻以及配合直流断路器,来降低短路电流的峰值、抑制电流的上升率和降低直流断路器中避雷器吸收能量,最终实现直流侧短路故障电流的快速清除。最后,利用PSCAD/EMTDC仿真验证该拓扑的有效性,仿真实验结果表明,所提新型直流限流器能够降低直流故障电流峰值(降幅达57.4%)、电流上升率(抑制率达50.3%)以及直流断路器中避雷器吸收能量。     

大容量逆变电源IGBT并联应用的仿真分析

该文针对逆变电源向大功率发展时受单管IGBT（绝缘门极双极型晶体管）电流容量限制的问题，受MOSFET（电力场效应晶体管）并联扩流成功应用的启发，提出采用多IGBT的并联技术，解决进一步提高逆变电源容量的难题。在分析IGBT工作机理基础上，给出了电路拓扑及其工作原理，并对并联器件产生的均流问题进行了重点分析，提出了相应的解决方法，推荐了IGBT并联应用的厚膜集成驱动电路。通过理论分析和计算机仿真结果表明：在大容量逆变电源中采用IGBT并联技术是有效可行的，它可以显著增加整机的电流容量，提高电源的有效功率。     

基于改进子模块的MMC-HVDC直流侧故障隔离研究

架空线路场合下的高压直流输电系统(HVDC)故障率较高。当前,混合式直流断路器存在容量小、成本高等问题,使得具备故障自清除能力的子模块成为解决系统直流侧故障的最佳解决方案,但上述方案使用了更多电力电子器件,带来了损耗增大,投资成本增加等问题。为此提出一种新型混合方式的模块化多电平换流器(MMC)子模块拓扑结构,在不影响自清除故障能力的前提下减少了所需电力电子器件,提高其经济性和直流侧故障隔离性能。首先给出了将新型子模块与传统半桥子模块在桥臂中合理搭配的设计方案;其次,探究了改进型拓扑结构极对极短路故障穿越机理及子模块构建的经济性性优化方法。最后,基于PSCAD/EMTDC平台搭建了双端MMC-HVDC模型,对提出的子模块性能及其混合型MMC性能进行仿真验证。结果表明,提出的改进子模块及相应的混合型MMC可快速阻断故障电流,具备良好直流故障隔离能力,且具有更好的经济性,在实际工程中上具有良好的应用前景。     

棒控系统电流故障典型案例分析

控制棒是核反应堆堆芯反应性控制的关键设备,核电厂控制棒驱动采用钩爪步进式磁力提升方式,棒控系统电源柜MDP模块提供驱动机构线圈的激励电流.为确保两个钩爪按照既定时序正确动作,当静态电流超限、动态过程电流或调节时间超限,MDP均发出电流故障报警.以钩爪啮合滞后、晶闸管击穿、控制电路故障、霍尔传感回路异常四种典型案例,结合...     

全柔性铰链平面并联微动机器人的有限元分析

介绍了并联机器人的特点及其应用,对全柔性铰链平面并联机器人建立了刚性模型,并采用闭环线型原理建立理论运动学线性模型（Jacobian矩阵）,用ANSYS软件对其进行有限元分析,得到有限元运动学模型（Jacobian矩阵值）,讨论两者关系,发现有限元模型比理论模型要精确.     

全桥式DC/AC/DC变换器的建模与仿真

研究高频DC/AC/DC开关变换器的控制系统优化问题.由于该变换器是典型的非线性系统,采用的PI控制器存在响应速度慢、超调量大等问题.为克服上述问题,优化高频DC/AC/DC开关变换器的暂态和稳态性能,采用了三极点、两零点控制器,解决了高频DC/AC/DC开关变换器的暂态和稳态性能差的问题.利用状态空间平均法及欧拉公式建立了全桥式DC/AC/DC开关变换器的动态小信号数学模型,根据所建立的数学模型采用频域法对系统进行设计,保证系统输出电压具有良好的电源调整率和负载调整率.仿真结果表明,三极点、两零点控制策略比传统PI控制具有更好的动态调节和稳态误差调节特性,超调量、调节时间等都得到了明显的改善,并为控制器设计优化提供了参考.     

英飞凌XMC4500控制的移相全桥ZVS DC/DC变换器

移相全桥变换器移相PWM信号的产生方式主要有模拟电路控制和数字电路控制两种.首先分析了数字控制与模拟控制对系统整体性能的影响;然后简要介绍了移相全桥DC/DC变换器PWM信号的特点,并提出了以XMC4500为基础的数字控制方案的硬件设计和双闭环控制流程;最后详细介绍了数字控制的具体实现过程,并通过样机试验证明了数字化控制的可行性.     

SCMA性能及仿真分析

快速的流量增长和无处不在的信道要求使探索下一代(5G)无线通信网络成为必然。在当前5G的研究领域,提出了非正交多范式转变的物理层技术。在所有现有的非正交的技术中,最近提出的稀疏码多址接入(SCMA)能达到一个更好的链路级性能。文中着重说明了SCMA产生的起因与基本性能,具体描述了系统模型与信号处理方法,阐释了它所采用的消息传递算法(Message Passing Algorithm)检测原理,并通过仿真以及与IDMA的比较说明它的优异性能。     

Parallel Critical Path Tracing——A Fault Simulation Algorithm for Combinational Circuits

Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to the parallel critical path tracing for functional block-level combinational circuits.If the word length of the host computer is m,then the parallel critical path tracing will be approximately m times faster than the original one.     

Traffic analysis and simulation performance of incompletehypercubes

The incomplete hypercube with arbitrary nodes provides far better incremental flexibility than the complete hypercube, whose size is restricted to exactly a power of 2. After faults arise in a complete hypercube system, it is desirable to reconfigure the system so as to retain as many healthy nodes as possible, often leading to an incomplete hypercube of arbitrary size. In this paper, the highest traffic density over links in an incomplete hypercube under uniform message distribution is shown to be bounded by 2 (messages per link per cycle), independent of its size and despite its structural nonhomogeneity. As a result, it is easily achievable to construct an incomplete hypercube with sufficient link communication capability where any potential points of congestion are avoided, ensuring high performance. Simulation results for the incomplete hypercube reveal that mean latency for delivering messages is roughly the same in an incomplete hypercube as in a compatible complete hypercube under both packet-switching and wormhole routing. The incomplete hypercube thus appears to be an attractive and practical architecture, since it shares every advantage of complete hypercubes while eliminating the restriction on the system size     

Parallel simulation based on conservative time windows: A performance study

The paper presents a Conservative Time Window (CTW) algorithm for parallel simulation of discrete event systems. The physical system to be simulated is partitioned into n disjoint sub-systems, each of which is represented by an object The CTW algorithm identifies a time window for each object, such that events occurring in each window are independent of events in other windows and thus they can be processed concurrently. The CTW algorithm was implemented on a shared memory multiprocessor, a Sequent Symmetry S81 with 16 processors. We measured performance of the CTW algorithm on two types of network topologies: feed-forward networks and networks with feedback loops. We used three metrics to measure performance: speed-up, average number of independent windows detected by the algorithm, and average number of events occurring in each window. We also investigated the impact of various event scheduling policies on performance. The results obtained show that the CTW algorithm produces good performance in many cases.     

A performance analysis exemplar: Parallel ray tracing

Among the many techniques in computer graphics, ray tracing is prized because it can render realistic images, albeit at great computational expense. Ray tracing's large computation requirements, coupled with its inherently parallel nature, make ray tracing algorithms attractive candidates for parallel implementation. In this paper we illustrate the utility and the importance of a suite of performance analysis tools when exploring the performance of several approaches to ray tracing on a distributed memory parallel system. These ray tracing algorithm variations introduce parallelism based on both ray and object partitions. Traditional timing analysis can quantify the performance effects of different algorithm choices (i.e. when an algorithm is best matched to a given problem), but it cannot identify the causes of these performance differences. We argue, by example, that a performance instrumentation system is needed that can trace the execution of distributed memory parallel programs by recording the occurrence of parallel program events. The resulting event traces can be used to compile summary stapistics that provide a global view of program performance. In addition, visualization tools permit the graphic display of event traces. Visual presentation of performance data is particularly useful, indeed, necessary for large-scale, parallel computations; assimilating the enormous volume of performance data mandates visual display.     

Parallel simulation of cyber-physical systems

Innovations in Systems and Software Engineering - Model-based design (MBD) in systems engineering is a well-accepted technique to abstract, analyze, verify, and validate complex systems. In MBD, we...     

Parallel simulation of statistical multiplexers

The simulation of high-speed telecommunication systems such as ATM (Asynchronous Transfer Mode) networks has generally required excessively long run times. This paper reviews alternative approaches using parallelism to speed up simulations of discrete event systems, and telecommunication networks in particular. Subsequently, a new simulation method is introduced for the fast parallel simulation of a common network element, namely, a work-conserving finite capacity statistical multiplexer of bursty ON/OFF sources arriving on input links of equal peak rate. The primary performance measure of interest is the cell loss ratio, due to buffer overflows. The proposed method is based on two principal techniques: (1) the derivation of low-level (cell level) statistics from a higher level (burst level) simulation and (2) parallel execution of the burst level simulation program. For the latter, atime-division parallel simulation method is used where simulations operating at different intervals of simulated time are executed concurrently on different processors. Both techniques contribute to the overall speedup. Furthermore, these techniques support simulations that are driven by traces of actual network traffic (trace-driven simulation), in addition to standard models for source traffic. An analysis of this technique is described, indicating that it offers excellent potential for delivering good performance. Measurements of an implementation running on a 32 processor KSR-2 multiprocessor demonstrate that, for certain model parameter settings, the simulator is able to simulate up to 10 billion cell arrivals per second of wallclock time.     

Active fault-tolerant control against actuator fault and performance analysis of the effect of time delay due to fault diagnosis

This paper discusses the problem of fault-tolerant control against actuator fault, derives the time spent at each steps in fault diagnosis which is called as the time delay due to fault diagnosis and quantitatively analyzes its effect on the faulty system’s performance. A fault diagnosis algorithm is first proposed. The proposed fault tolerant controller is designed to guarantees that all signals in the closed-loop system are semi-globally uniformly ultimately bounded, where the controller singularity is avoided without projection algorithm. What’s more, the analytical expression of the time delay is derived strictly. Further, the quantitative analysis of system performance which is degraded by the time delay is developed, and the conditions that the magnitudes of the faults should be satisfied such that the faulty system controlled by the normal controller remains bounded even stable during the time delay are derived. In addition, the corresponding solution to the adverse effect of the time delay is proposed. Finally, an experimental test shows that the proposed control algorithm has a very reliable efficiency.