FIR滤波器的DSP实现

介绍了FIR滤波器的基本结构及设计方法,结合实例,给定滤波器的数字指标。利用FDATool来确定FIR滤波器抽头系数。基于DSP平台,采用MATLB产生待滤波输入信号导入到用C语言实现的FIR低通滤波器中,并且在CCS上仿真,对仿真结果与理论值进行比较。波形仿真结果和理论值相吻和表明设计的系统是正确、稳定的。不同的应用场合,FIR滤波器要求有不同性能,只要修改本设计中滤波器的系数,就可以实现性能不同的FIR滤波器。     

IIR滤波器的DSP实现

IIR滤波器用较少阶数就获得较高的频率选择特性。根据滤波器的技术指标,采用FDATool工具来设计阶数最小的滤波器,导出滤波器的抽头系数;然后用DSP汇编语言编程,实现IIR算法;用MATLAB产生合成输入信号,导入滤波系统;最后,用CCS软件观察滤波前后的波形变化。波形仿真结果和理论值相吻合。     

LMS自适应算法设计FIR,IIR数字滤波器的应用及比较

简要介绍了FIR，IIR数字滤波器的特点，在此基础上应用基于自适应模型的LMS算法对FIR，IIR数字滤波器进行了系数综合，并通过Matlab 6．5计算机仿真比较了不同抽头数时，两种类型滤波器效果的差别，给出了一些重要结论。从计算机仿真结果可以看出，当滤波器抽头数相同时，IIR滤波器具有更好的通带和阻带特性。而随着抽头数目的增加，FIR滤波器的性能可以得到很大改善。当抽头数目足够大时，两种滤波器性能趋于一致。值得指出的是，LMS算法用于FIR滤波器的计算量明显小于相同抽头数的IIR滤波器，因而收敛较快。     

基于FPGA的FIR数字滤波器设计与仿真

采用改进并行分布式算法设计了一种16抽头FIR数字低通滤波器,首先用Matlab工具箱中的FDATool设计滤波器系数,然后使用硬件描述语言Verilog HDL和原理图,实现了子模块和系统模块设计,在Matlab与QuartusII中对系统模块进行联合仿真。仿真结果表明,设计系统性能稳定,滤波效果良好,且实用性较强。     

基于循环缓冲区FIR滤波器的设计

数字滤波技术主要包括滤波器设计及滤波过程的实现两方面内容。文中阐述了FIR滤波器基本结构,结合实例用Matlab来确定FIR滤波器系数,分析了循环缓冲区算法原理。在该算法的基础上,结合设计的滤波器实现对输入混合信号的FIR数字滤波,最后给出了滤波前后输入输出信号波形仿真。     

基于FPGA的FIR滤波器的设计与实现

本文分析了FIR滤波器的结构特点和基本原理,基于Matlab用窗函数法对FIR滤波器进行设计并在Simulink中进行系统仿真.最后,在FPGA中实现并利用SignalTap Ⅱ逻辑分析器对设计进行测试验证,测试结果与仿真结果一致.     

基于FPGA的半并行FIR滤波器设计

为了提高FIR滤波器的运算速度和降低资源消耗,本文提出了一种新颖的半并行FIR滤波器设计方法。该方法有固定的延时．可以根据滤波器抽头数的不同,得到不同的最高数据输入速率。仿真结果表明,该滤波器设计方法在高速数字下变频器的设计中有较好的性能．并且通过优化设计．可以在一个FPGA实现多个滤波器模块。     

基于FPGA的半并行FIR滤波器设计

为了提高FIR滤波器的运算速度和降低的资源消耗,提出了一种新颖的半并行FIR滤波器设计方法,该方法有同定的延时,可以根据滤波器抽头数的不同,得到不同的最高数据输入速率。仿真结果表明,该滤波器设计方法存高速数字下变频器的设计中有较好的性能,并且通过优化设计,可以任一个FPCA实现多个该滤波器模块。     

基于FPGA的串行多阶FIR滤波器设计

FIR滤波器的设计分为滤波器系数计算和滤波器结构的具体两个部分。为说明使用FPGA实现FIR的灵活性,文中列举了一个多阶串行FIR滤波器实例,并给出主要的源代码和相关模块的时序和功能说明,最后使用Matlab和Quartusii联合仿真验证了FPGA硬滤波器工程的正确性。     

基于FPGA的FIR数字滤波器的优化设计

提出采用正则有符号数字量（CSD）编码技术实现FIR滤波器。首先分析了FIR数字滤波器理论及常用设计方法的不足,然后介绍了二进制数的CSD编码技术及其特点,给出了其于CSD编码的定点常系数FIR滤波器设计过程,使用VHDI,语言实现了该常系数滤波器的行为描述。最后在Max＋PlusⅡ环境下进行实验仿真和验证,与DA和2C编码算法比较结果表明,用CSD编码技术实现的滤波器可以有效提高运算速度并降低FPGA芯片的面积占用。     

A programmable FIR digital filter using CSD coefficients

An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-μm CMOS technology     

FIR digital filter-based ZCDPLL for carrier recovery

The objective of this work is to analyse the performance of the newly proposed two-tap FIR digital filter-based first-order zero-crossing digital phase-locked loop (ZCDPLL) in the absence or presence of additive white Gaussian noise (AWGN). The introduction of the two-tap FIR digital filter widens the lock range of a ZCDPLL and improves the loop’s operation in the presence of AWGN. The FIR digital filter tap coefficients affect the loop convergence behaviour and appropriate selection of those gains should be taken into consideration. The new proposed loop has wider locking range and faster acquisition time and reduces the phase error variations in the presence of noise.     

一种FIR滤波器的FPGA实现

数字滤波是语音与图像处理和模式识别等应用中的一种基本的数字信号处理部件。文中提出了一种采用FPGA器件并利用窗函数实现线性FIR数字滤波器的方案,使用Xilinx公司的XCS10FPGS器件设计了一个8阶8位FIR滤波器,阶数和位数以及滤波器特性均可方便地更改。     

Blind input, initial state, and system identification of SIMO Laguerre systems

Laguerre filters have infinite impulse responses (IIRs) but with finite tapped delay-line parameterizations. This paper investigates subspace-based blind identification of Laguerre filter tap coefficients, the internal filter state, and the input, given only noisy observations of the output. This paper deals only with single-input, multiple-output (SIMO) Laguerre models. A state space model for the SIMO Laguerre system is derived from which blind estimation algorithms are developed. As in the finite impulse response (FIR) case, the Laguerre filter taps coefficients can be estimated from the column space of a certain Hankel matrix constructed from noisy output observations, whereas the internal state and input can be estimated from the row space by exploiting state space structure. While not exactly uniquely identifiable, conditions are given for which the tap coefficients, the internal state, and the input can be determined to within a multiplicative scalar factor.     

A 19.2 GOPS mixed-signal filter with floating-gate adaptation

We have built a 48-tap, mixed-signal adaptive FIR filter with 8-bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the least mean square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed-signal multipliers, and adapt the tap coefficients using pulse-based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in a 0.35-/spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200 MHz, and consumes 20 mW providing a 6-mA differential output current.     

Charge-domain FIR sampler with programmable filtering coefficients

A charge-domain sampling technique for realization of mixed-mode finite-impulse response (FIR) filters is presented. The method is based on weighting signal current samples integrated into a sampling capacitor with a set of parallel digitally controlled current-mode switches each carrying a unit current element. The fine achievable resolution and digital controllability of the filter tap coefficients allows realization of advanced programmable FIR filtering functions embedded into high-frequency signal sampling. Circuit-level simulation results of an example 50-MHz IF-sampler with a built-in 22-tap complex bandpass sinc/sup 3/ FIR function in 0.35-/spl mu/m CMOS are shown, demonstrating the feasibility of the presented method.     

A mixed-signal approach to high-performance low-power linearfilters

We present a new approach to the design of high-performance low-power linear filters. We use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. To demonstrate the effectiveness of our approach, we have built a 16-tap 7-b 200-MHz mixed-signal finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The filter uses synapse pFETs to store the analog tap coefficients, electron tunneling and hot-electron injection to modify the coefficient values, digital registers for the delay line, and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap coefficients. The measured maximum clock speed is 225 MHz; the measured tap-multiplier resolution is 7 b at 200 MHz. The total die area is 0.13 mm². We can readily scale our design to longer delay lines     

Efficient recursive realizations of FIR filters

A class of efficient filter structures is proposed which uses a recursive realization of an FIR filter. The structures are in some sense a generalization of the frequency sampling structure, but they are more versatile and arise from a time-domain rather than frequency-domain argument. The new structure has a tap out of every block delay, and the length of the block delay is the length of each piecewise section of the time-domain approximation. The number of taps, filter coefficients, and the amount of arithmetic are proportional to the number of piecewise sections, not to the actual filter length or order. This filter is particularly efficient when a long-length filter can be approximated by a few piecewise sections, which is the case for many practical filters.This research was supported by NSF grant ECS 81-00453.     

FIR filters with field-programmable gate arrays

Distributed arithmetic techniques are the key to efficient implementation of DSP algorithms in FPGAs. The distributed arithmetic process is briefly described. A representative DSP design application in the form of an 8 tap FIR filter is offered for the Xilinx XC3042 field programmable logic array (FPGA). The design is presented in sufficient detail—from filter specifications via filter design software through detailed logic of salient data and control functions to obtain a realistic placing and routing of configurable logic block (CLBs) and in/out block (IOBs) components for simulation verification and performance evaluation vis-a-vis commercially available dedicated 8 tap FIR filter chips.