A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-linearchitecture

A 16-Mb dynamic RAM has been designed and fabricated using 0.5-μm CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3-μm² in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4×17.38 (93.85) mm² to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time     

A 5-V-only operation 0.6-μm flash EEPROM with row decoder schemein triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6-μm triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0×1.8 μm² has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11×6.95 mm², and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm² by using the minimal cell size (2.0×10 μm²)     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

Power performance of InP-based single and double heterojunctionbipolar transistors

The microwave and power performance of fabricated InP-based single and double heterojunction bipolar transistors (HBTs) is presented. The single heterojunction bipolar transistors (SHBTs), which had a 5000 Å InGaAs collector, had BV_CEO of 7.2 V and J_Cmax of 2×10⁵ A/cm². The resulting HBTs with 2×10 μm² emitters produced up to 1.1 mW/μm2 at 8 GHz with efficiencies over 30%. Double heterojunction bipolar transistors (DHBTs) with a 3000-Å InP collector had a BV_CEO of 9 V and J_{c max} of 1.1×10⁵ A/cm², resulting in power densities up to 1.9 mW/μm² at 8 GHz and a peak efficiency of 46%. Similar DHBTs with a 6000 Å InP collector had a higher BV_CEO of 18 V, but the J _{c max} decreased to 0.4×10⁵ A/cm² due to current blocking at the base-collector junction. Although the 6000 Å InP collector provided higher f_max and gain than the 3000 Å collector, the lower J_{c max} reduced its maximum power density below that of the SHBT wafer. The impact on power performance of various device characteristics, such as knee voltage, breakdown voltage, and maximum current density, are analyzed and discussed     

A new cryogenic CMOS readout structure for infrared focal planearray

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm². Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×10⁸ electrons, a maximum transimpedance of 1×10⁹ Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's     

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is fiver per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5 μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7×8 μm² and the chip size is 5.55×7.05 mm². The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC     

A 14 ns 256 K×1 CMOS SRAM with multiple test modes

A methodology to enter and exit from test modes in asynchronous static RAMs (SRAMs) is presented. This chip is fabricated in a 0.7 μm twin-tub, single-poly, double-metal technology on p/p⁺ epitaxial substrate. To prevent hot-electron degradation, a voltage regulator is used in the memory matrix, with the cascoding technique applied in the periphery. Circuits were implemented against voltage bumps and data glitching on the output. A small cell size of 5.1×13.7 μm² and a chip size of 3.9×9.5 mm² have been achieved     

Room temperature far infrared (8~10 μm) photodetectors usingself-assembled InAs quantum dots with high detectivity

Room temperature operation of far-infrared detectors made of self-assembled quantum dots embedded in the channel region of modulation-doped heterostructures is demonstrated. At room temperature, the detector shows a low dark current ranging in the nano-amperes at a bias voltage of 10 V. After the optimization of the separation between the quantum dot region and the 2DEG, a peak responsivity of 5.3 A/W is obtained at 9.0 μm. The high detectivities of 6×10⁸ and 5×10¹⁰ cmHz^1/2/W are obtained at room temperature and 80 K, respectively     

A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

A programmable analog neural network chip

A generic chip is implemented in CMOS to facilitate studying networks by building them in analog VLSI. By utilizing the well-known properties of charge storage and charge injection in a novel way, the authors have achieved a high enough level of complexity (>10³ weights and 10 bits of analog depth) to be interesting, in spite of the limitation of a modest 6.00×3.5-mm² die size required by a multiproject fabrication run. If the cell were optimized to represent fixed-weight networks by eliminating weight decay and bidirectional weight changes, the density could easily be increased by a factor of 2 with no loss in resolution. Once a weight change vector has been written to the RAM cells, charge transfers can be clocked at a rate of 2 MHz, corresponding to peak learning rates of 2×10⁹ weight changes/second and exceeding the throughput of `neural network accelerators' by two orders of magnitude     

A Reed-Solomon product-code (RS-PC) decoder chip for DVDapplications

In this paper, a Reed-Solomon Product-Code (RS-PC) decoder for DVD applications is presented. It mainly contains two frame-buffer controllers, a (182, 172) row RS decoder, and a (208, 192) column RS decoder. The RS decoder features an area-efficient key equation solver using a novel modified decomposed inversionless Berlekamp-Massey algorithm. The proposed RS-PC decoder solution was implemented using 0.6 μm CMOS single-poly double-metal (SPDM) standard cells. The chip size is 4.22×3.64 mm² with a core area of 2.90×2.88 mm ^mm², where the total gate count is about 26 K. Test results show that the proposed RS-PC decoder chip can support 4×DVD speed with off-chip frame buffers or 8×DVD speed with embedded frame buffers operating at 3 V     

High peak tunnel current densityGa0.47In0.53As Esaki diodes

High peak current density Ga_0.47In_0.53As interband tunnel diodes were fabricated by metal organic molecular beam epitaxy. A room temperature peak-to-valley current ratio of 16 and a peak tunnel current density of 9.2 kA/cm² were obtained in diodes doped to ~3×10¹⁹cm³ on both n-type and p-type sides. A peak-to-valley current ratio of 3.8, and a peak tunnel current density of 93.2 kA/cm² were obtained in diodes doped to ~10²⁰ cm^-3 on both n-type and p-type sides     

Performance enhancement of GaInP/GaAs heterojunction bipolarphototransistors using dc base bias

GaInP-GaAs heterojunction bipolar phototransistors grown by metal organic vapor phase epitaxy (MOVPE) and operated with frontside optical injection through the emitter are reported with high optical gain (<88) and record high frequency performance (28 GHz). Heteropassivation of the extrinsic base surface is employed using a depleted GaInP emitter layer between the nonself-aligned base contact and the emitter mesa. The phototransistor's performance is shown to improve with increasing dc base bias in agreement with predictions of a recently reported Gummel-Poon model. Experimental results are reported for devices with optical active areas of 10×10 μm², 20×20 μm², and 30×30 μm², with peak measured cutoff frequencies of 28.5, 23.1, and 18.5 GHz, respectively, obtained at collector current densities between 2×10 ³ and 6×10³ A/cm²     

An 8-bit-resolution, 360-μs write time nonvolatile analog memorybased on differentially balanced constant-tunneling-current scheme(DBCS)

This paper describes a fast and accurate nonvolatile analog memory (NVAM) and its programming scheme. Both constant programming rate and single-pulse programmability have been achieved, which drastically enhance programming speed and accuracy. A prototype chip containing 8×128 NVAM cells (cell size of 9×13.6 μm²) has been fabricated using 0.8-μm CMOS. Each cell is measured to store more than eight bit levels within 360 μs     

An 18-ns 1-Mbit CMOS SRAM

A 1-Mb (256 K×4 b) CMOS static random-access memory with a high-resistivity load cell was developed with 0.7-μm CMOS process technology. This SRAM achieved a high-speed access of 18 ns. The SRAM uses a three-phase back-bias generator, a bus level-equalizing circuit and a four-stage sense amplifier. A small 4.8×8.5-μm² cell was realized by the use of a triple-polysilicon structure. The grounded second-polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size measures 7.5×12 mm²     

Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

A 55-ns 16-Mb DRAM with built-in self-test function usingmicroprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55-μm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm² chip area was attained by implementing 4.05-μm² storage cells. The installed ROM was composed of 18 words×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm² and the area overhead is about 1%, it proves to be promising for large-scale DRAMs     

Emission cross sections and spectroscopy of Ho3+ laserchannels in KGd(WO4)2 single crystal

The spectroscopic properties of Ho³⁺ laser channels in KGd(WO₄)₂ crystals have been investigated using optical absorption, photoluminescence, and lifetime measurements. The radiative lifetimes of Ho³⁺ have been calculated through a Judd-Ofelt (JO) formalism using 300-K optical absorption results. The JO parameters obtained were Ω₂=15.35×10^-20 cm², Ω ₄=3.79×10^-20 cm², Ω₆ =1.69×10^-20 cm². The 7-300-K lifetimes obtained in diluted (8·10¹⁸ cm^-3) KGW:0.1% Ho samples are: τ(⁵F₃)≈0.9 μs, τ( ⁵S₂)=19-3.6 μs, and τ(⁵F₅ )≈1.1 μs. For Ho concentrations below 1.5×10²⁰ cm^-3, multiphonon emission is the main source of non radiative losses, and the temperature independent multiphonon probability in KGW is found to follow the energy gap law τ_ph ^-1(0)=βexp(-αΔE), where β=1.4×10^-7 s^-1, and α=1.4×10³ cm. Above this holmium concentration, energy transfer between Ho impurities also contributes to the losses. The spectral distributions of the Ho³⁺ emission cross section σ_EM for several laser channels are calculated in σ- and π-polarized configurations. The peak a σ_EM values achieved for transitions to the ⁵I₈ level are ≈2×10^-20 cm² in the σ-polarized configuration, and three main lasing peaks at 2.02, 2.05, and 2.07 μm are envisaged inside the ⁵I₇→⁵I₈ channel     

32×32 ultraviolet Al0.1Ga0.9N/GaN p-i-nphotodetector array

We report the fabrication and performance of a 32×32 Al_0.1Ga_0.9N-GaN ultraviolet p-i-n photodetector array. The devices exhibit very low dark current, the mean dark current density is ~4 nA/cm² at 5-V reverse bias, and the dark current distribution is very uniform (~98% of the devices exhibit dark current density <90 nA/cm²). Owing to the design of the p-Al_0.13Ga_0.87N window layer, the external quantum efficiency is as high as 72% at 357 nm. The photocurrent distribution is also presented. The detectivity is estimated to be as high as 8×10 ¹⁴ cm·Hz^1/2·W^-1