硅微机械平面电感的衬底效应

提出了一种品质因数(Q)的计算方法,分析了对于平面螺旋电感Q值产生决定性影响的各种因素.在微机械电感传统模型的基础上对涡流效应产生的寄生电阻和有损衬底电容进行了细致的研究,并且得到了理论结果.研究结果表明,Q值的大小与几何参数和工作频率均有关.通过理论分析和计算,可以得到结构优化的方法.     

硅微机械平面电感的衬底效应

提出了一种品质因数(Q)的计算方法,分析了对于平面螺旋电感Q值产生决定性影响的各种因素.在微机械电感传统模型的基础上对涡流效应产生的寄生电阻和有损衬底电容进行了细致的研究,并且得到了理论结果.研究结果表明,Q值的大小与几何参数和工作频率均有关.通过理论分析和计算,可以得到结构优化的方法.     

硅微机械平面电感的衬底效应

提出了一种品质因数(Q)的计算方法，分析了对于平面螺旋电感Q值产生决定性影响的各种因素。在微机械电感传统模型的基础上对涡流效应产生的寄生电阻和有损衬底电容进行了细致的研究，并且得到了理论结果。研究结果表明，Q值的大小与几何参数和工作频率均有关，通过理论分析和计算，可以得到结构优化的方法。     

硅微机械悬浮结构电感的设计与制作工艺研究

本文系统分析了影响平面螺旋电感Q值的主要因素,并制作出一种应用于射频通信的硅微机械悬浮结构电感.在考虑趋肤效应、涡流损耗等高频电磁场效应对电感Q值的影响后,获得了微机械电感的简化电学模型,得到了具有较高Q值电感的优化结构.在制作硅微机械电感的工艺过程中,采用多孔硅作为牺牲层材料,将螺旋结构铝线圈制作在二氧化硅薄膜上,在使用添加了硅粉和过硫酸铵的TMAH溶液释放牺牲层之后,得到设计值为4nH的悬浮结构微机械平面螺旋电感.实验结果证明,整个工艺流程可靠,并与CMOS工艺兼容.     

高性能螺线管微电感的制作

利用MEMS技术制作了高性能的空芯螺线管型射频微机械电感.这种微电感采用铜线圈以减小线圈寄生电阻,整个微电感的面积是880μm×350μm,与平面螺旋型微电感相比,有效地节省了芯片面积.测试结果表明,微电感在较宽的工作频率范围内具有高Q值,微电感最大Q值为38(@6GHz),对应的电感量为1.82nH.     

高性能螺线管微电感的制作

利用MEMS技术制作了高性能的空芯螺线管型射频微机械电感.这种微电感采用铜线圈以减小线圈寄生电阻,整个微电感的面积是880μm×350μm,与平面螺旋型微电感相比,有效地节省了芯片面积.测试结果表明,微电感在较宽的工作频率范围内具有高Q值,微电感最大Q值为38(@6GHz),对应的电感量为1.82nH.     

RF平面螺旋微电感的物理模型

为了在RF频率域内准确模拟RF平面螺旋微电感的性能，讨论了一种计算RF平面螺旋微电感的物理模型，此模型采用Greenhouse法计算微电感的电感量，在计算微电感Q值时，考虑了诸如涡流、衬底电阻及各种寄生电容等因素，寄生电容包括电感与终端引出层间的交叉电容，电感与衬底间的电容，衬底电容等。这种模型可以计算不同布局及参数的微电感，为微电感的设计及其性能的优化提供了一种很好的方法。     

陶瓷基板上的集成微电感模型与制作

对陶瓷基板上的集成微电感模型进行了分析.由于陶瓷基板的介电常数比Si基板低,电阻率极高,因此衬底损耗大大减小,从而有效提高了电感的Q值.同时,为了更好进行对比,研究中采用相同工艺在陶瓷基板和Si基板上同批制作了集成电感,两者的结构参数完全一致.测试结果表明,两者的电感值L基本相同,然而陶瓷基板上集成微电感Q值的峰值要比Si基板集成微电感高7左右,Si基板上Q值峰值在5 GHz以下,而陶瓷基板集成微电感的Q值峰值在10 GHz左右.     

RF平面螺旋微电感计算机模拟研究

应用Greenhouse法对RF平面螺旋微电感进行了计算机模拟,探明了微电感品质因数Q值在高频域内的变化规律,得出了微电感金属层厚度、线宽、线间距及线圈数与RF平面螺旋微电感Q值的对应关系。研究发现,RF平面螺旋微电感的Q值在高频域内随频率增加而呈现先升高后下降的趋势,Q值存在峰值;微电感Q值在某一频率范围内随微电感金属层厚度、线宽的增加而增大;随线间距的增加,微电感的低频性能下降而高频(>1GHz)性能升高;当微电感直径一定时,随线圈数的增加,Q值有下降的趋势。     

基于玻璃衬底的三维电感器件的仿真与实现

为了实现射频电子系统中对高品质因数电感的迫切需求,首先基于玻璃衬底建立了三维电感的电磁仿真模型,并从槽深度、线宽、线间距、电感线圈内径和匝数等方面对电感的电感值及其品质因数Q进行了参数化的仿真研究。仿真结果表明,玻璃衬底上三维电感的最优参数组合为槽深度120～150μm、线宽30～40μm、线间距30～60μm、电感线圈内径250μm和1.5～3圈的电感匝数。在光敏玻璃衬底上利用玻璃通孔技术进行三维电感的制作并对完成的电感进行了测试。电感测得的最大Q值均大于55,该测试结果与仿真结果相一致,验证了三维电感仿真模型的有效性和制造工艺的可实施性。     

High-Q factor three-dimensional inductors

In this paper, the great flexibility of three-dimensional (3-D) monolithic-microwave integrated-circuit technology is used to improve the performance of on-chip inductors. A novel topology for high-Q factor spiral inductor that can be implemented in a single or multilevel configuration is proposed. Several inductors were fabricated on either silicon substrate (/spl rho/ = 30 /spl Omega/ /spl middot/ cm) or semi-insulating gallium-arsenide substrate demonstrating, more particularly, for GaAs technology, the interest of the multilevel configuration. A 1.38-nH double-level 3-D inductor formed on an Si substrate exhibits a very high peak Q factor of 52.8 at 13.6 GHz and a self-resonant frequency as high as 24.7 GHz. Our 4.9-nH double-level GaAs 3-D inductor achieves a peak Q factor of 35.9 at 4.7 GHz and a self-resonant frequency of 8 GHz. For each technology, the performance limits of the proposed inductors in terms of quality factor are discussed. Guidelines for the optimum design of 3-D inductors are provided for Si and GaAs technologies.     

Miniature 3-D inductors in standard CMOS process

The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-μm one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f_SR of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q_max. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced     

The modeling, characterization, and design of monolithic inductorsfor silicon RF IC's

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs     

Add-on Cu/SiLKTM module for high Q inductors

Thick Cu single damascene inductors are integrated on top of a standard aluminum three-levels-of-metal (3LM) back-end of line (BEOL) silicon process. The obtained Q factors are more than four times higher than Q factors of the inductors of the same geometry processed in the Al 3LM BEOL. For an inductor of 3 nH designed for 2-GHz frequency applications and fabricated in thick Cu/SiLK^TM1 as an add-on module, a Q factor of ~24 is reached. A compact two-section lumped element SPICE model is proposed and validated for both inductors in thick Cu/SiLK^TM and inductors in standard aluminum 3LM BEOL     

Sub-nH Inductor Modeling and Design in 90-nm CMOS Technology for Millimeter-Wave Applications

Inductor design is an important issue in millimeter-wave CMOS circuits. In these frequencies the required inductance is very small and hence special structure is required for inductors. The quality factor is the most important design parameter for these inductors, especially in CMOS process. To incorporate these inductors in circuit simulation, a simple lumped model is necessary. This work proposes a simple and accurate model, developed for design and optimization of such inductors. This model is based on quasi-transverse-electromagnetic-mode assumption. To increase the model accuracy we have separately modeled the short-end section of the inductor. Model parameters are calculated using reported analytic equations and some new empirical equations. Using this model we have designed and optimized a 250-pH inductor with different shield layers, for STMicroelectronics 90-nm digital CMOS process. The accuracy of the model parameters and the evaluation of the model has been carried out using 2-D and method-of-momentss electromagnetic solvers in Advanced Design System, with the substrate modeled using foundry design kit data.     

Improvement of the quality factor of RF integrated inductors bylayout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency     

S-parameter formulation of quality factor for a spiral inductor in generalized two-port configuration

This paper formulates various quality (Q) factors associated with the applications of on-chip spiral inductors to radio-frequency integrated circuits using S-parameters. The formulations start with the Q factor of a spiral inductor in a generalized two-port configuration based on a new complex-power approach and then extend to the Q factors of a tank and matching circuits that use the spiral inductors. In the demonstration, the two-port S-parameters for a series of CMOS spiral inductors have been measured to further generate such various Q factors for a many-sided evaluation of the inductor performance.     

MMIC用多层磁膜电感研究

采用磁控溅射生长磁膜工艺,结合BCB(苯并环丁烯)平坦化技术,首次制作了"金属线圈/磁膜/金属线圈(M/F/M)"和"磁膜/金属线圈/磁膜/金属线圈(F/M/F/M)"两种结构的多层磁膜电感,整个工艺与标准MMIC工艺兼容.在2 GHz处,"金属线圈/磁膜/金属线圈"结构电感的电感量为7.5 nH,品质因数为7.17,...     

Robust CMOS Micromachined Inductors With Structure Supports for Gilbert Mixer Matching Circuits

In this brief, three novel structure supports for on-chip CMOS-based micromachined inductors are proposed to improve mechanical stability. The inductors are fabricated using a two-step maskless post-CMOS process. A 3-D electromagnetic inductor simulation model is established for performance analysis of the inductors before fabrication. The proposed inductors are applied in the matching network of the double-balanced Gilbert mixer to improve the performance and mechanical reliability for mobile communication. The mixers with and without micromachined process inductors are fabricated in a 0.5-mum CMOS process. The measurement results show an 18.6% increase in the conversion gain, a 31.7% improvement in the third intercept point (IIP3), and a 25.3% reduction in the noise figure.     

片上螺旋电感集总模型中衬底因子的分析与拟合

石英、高阻SOI、高阻硅等衬底上实现的电感具有比低电阻率衬底的电感更优的高频性能,因而研究基于不同衬底的电感性能,并在高频模型中进行精确的衬底因子表征就显得十分重要.综合考虑高频下的趋肤效应和邻近效应及衬底电磁损耗对电感性能的影响,实现了片上螺旋电感的集总元件模型,并通过与SOI、石英衬底的电感仿真参数及高阻硅衬底的电感测试参数进行了模型验证,结果表明,该模型拟合的S参数及Q值曲线能与仿真及测试结果吻合,同时模型中衬底因子的提取值与衬底性质相符合,因而该模型适用于片上电感的模拟与设计.