Statistical properties of the LMS fourier analyzer in the presence of frequency mismatch

The statistical performances of the conventional adaptive Fourier analyzers, such as the least mean square (LMS), the recursive least square (RLS) algorithms, and so forth, may degenerate significantly, if the signal frequencies given to the analyzers are different from the true signal frequencies. This difference is referred to as frequency mismatch (FM). We analyze extensively the performance of the conventional LMS Fourier analyzer in the presence of FM. Difference equations governing the dynamics and closed-form steady-state expression for the estimation mean square error (MSE) of the algorithm are derived in detail. It is revealed that the discrete Fourier coefficient (DFC) estimation problem in the LMS eventually reduces to a DFC tracking one due to the FM, and an additional term derived from DFC tracking appears in the closed-form MSE expression, which essentially deteriorates the performance of the algorithm. How to derive the optimum step size parameters that minimize or mitigate the influence of the FM is also presented, which can be used to perform robust design of step size parameters for the LMS algorithm in the presence of FM. Extensive simulations are conducted to reveal the validity of the analytical results.     

基于图像运动检测的子场编码优化算法

针对等离子显示器中运动图像产生的动态伪轮廓现象,提出了一种基于图像运动检测的子场编码优化算法。该算法在分析常用动态伪轮廓和运动补偿算法的基础上,通过检测图像数据的变化差值判断图像的运动状态,并通过图像运动状态选择不同的显示灰度构成方式:静态图像选择全灰度级编码,动态图像选择较少灰度级编码,通过优化编码方式消除图像的动态伪轮廓。实验表明,算法减少了不同运动速度的图像因算法引起的人工纹理,保证了静态图像的显示细节,达到改善显示图像画质的目的。此外,该算法还具有处理速度快,易于硬件实现等优点。     

On Decorrelated Fast Cipher

Decorrelated Fast Cipher(DFC) is a candidate for the Advanced Encryption Standard (AES). It is shown that the cryptographic properties of the confusion permutation of DFC are weak in this paper. With the same F-function of DFC, a Feistel cipher VDFC which has no resistance against differential cryptanalysis is constructed. This demonstrates the importance of the key addition into DFC sufficiently. As a result, DFC may not be qualified candidate for the AES.     

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-/spl mu/m CMOS process with core area of 0.16 mm/sup 2/. Power consumption is 15 mW @ 378 MHz with 1.8-V supply voltage.     

彩色PDP动态假轮廓的评价方法--相对比值法

为减小彩色等离子体显示器(PDP)的动态假轮廓(DFC),在分析DFC产生的主要原因和距离法评价DFC的基础上,根据人眼视觉对亮度响应的特性,提出了一种评价DFC的新方法———相对比值法。该方法认为人的视觉是对DFC的相对量敏感,因此,定义任一灰度级的DFC为该灰度级和无DFC的灰度级之间的DFC之和与该灰度级的比值。通过对不同子场编码DFC的计算,结果表明:增加子场数、改变子场顺序、采用斜坡上升编码(SIC)方法,都会使动态假轮廓减轻。根据图像的灰度直方图,对各灰度级选择合适的子场组合,可以进一步优化DFC。     

一种低抖动噪声的PDP动态假轮廓改善方法

为降低等离子体显示器(PDP)动态假轮廓(DFC)改善中的抖动噪声,提出了一种抖动区域宽度自适应变化并融合孤立像素点分离的随机抖动改善DFC方法.首先分析DFC干扰条纹的特性,得到符合视觉特性的DFC评测方法;然后根据DFC的严重程度计箅相应的抖动区域宽度,采用融合孤立像素点分离的随机抖动方法实现未被选取的灰度级.仿真...     

DFC++ Processing Framework Concept

Development of modern Software Defined Radio (SDR) based communication systems can be accelerated significantly by the use of processing frameworks. The evolution of SDR and the involved departure from digital representations of classical radio architecture towards more abstract software systems raises new requirements of increased flexibility and versatility. The proposed Data Flow Control for C++ (DFC++) processing framework concept addresses those requirements by employing modern programming techniques and flow control mechanisms to allow for variable data rates, dynamic paths, and flexible component designs. Another important trend is the integration of various embedded platforms in the software radio domain. The rapidly increasing performance and efficiency of embedded processors enables the deployment of SDR systems in more space and power constrained environments. Therefore covering a heterogeneous hardware selection becomes increasingly important for processing frameworks. By relying exclusively on C++ and minimizing external dependencies, DFC++ is specifically aiming for excellent portability and adaptability to support a wide range of current and future software radio projects while maintaining high performance and ease of use. This paper introduces the key aspects of the DFC++ concept and implementation with focus on the reference pointer based data transport mechanisms responsible for the propagation of user data between different processing components.     

Application of advanced microelectronics to large-scalecommunication equipment-compact and maintenance-free TDMA equipment

An architecture is proposed for TDMA (time division multiple access) equipment and functional-module realization in microelectronics to increase reliability and to reduce hardware size and development time. The approach described basically involves digitization of analog circuits (allowing their realization using digital LSI circuits) and analog IC implementation for high-speed circuits. In order to use general-purpose LSI circuits and ICs, TDMA equipment is reconfigured into a hardware-oriented and simplified architecture. Using this architecture and optimal function assigning to each module, six types of general-purpose synchronization unit LSI circuits have been developed in addition to eleven types of LSI circuits and ICs, i.e. three types of digital LSI circuits, four types of MAICs (monolithic analog ICs), and four types of HICs (hybrid ICs) for a burst modem. As a result of this LSI circuit and IC implementation, the hardware size of TDMA equipment has been reduced to one-fifth of the conventional size, and maintenance-free capability has been achieved     

A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation

A digital-to-frequency converter (DFC) assisted by a built-in-self-measurement mechanism is presented. It demonstrates the capability to overcome oscillator pulling that is caused by the high-speed digital frequency-tuning signal that is fed into the DFC’s digitally-controlled-oscillator (DCO), thereby allowing the DFC to accommodate high-rate modulating data. Thus, by placing replica images and quantization noise far away from the transmitted carrier, the presented DFC is suitable for wireless applications having the most demanding spectral mask requirements, without necessitating RF filtering in the transmitter’s signal path. The proposed solution, designed with minimum overhead, reduces the extent of injection pulling experienced by the digitally controlled oscillator (DCO) due to ΣΔ dithering applied to its capacitor bank by adjusting the phase between the aggressor and victim signals through a digitally controlled delay (DCD) line. The proposed calibration and compensation scheme for the DCD is autonomous and simple computationally. The proposed solution has been demonstrated in a transmitter of a commercial cellular CMOS system-on-chip (SoC).     

High-performance direct-frequency converters controlled bypredictive-current loop

Two predictive space-vector control strategies for direct-frequency converter (DFC) structures are presented. Both algorithms require output-current feedback in order to decide the next best state of the power converter. The performance of the control techniques is compared with a high-performance fictitious-link DFC. Computer simulation using Microsim PSpice 5.3 is used to examine the operation of the DFC converter algorithms. The evaluation is performed for a wide-operational output frequency and includes input/output-voltage ratio, commutation frequency, input-current balance, input-current total harmonic distortion (THD) and input power factor. From these results, the high performance exhibited by the proposed algorithms is verified     

A scheduling scheme with Dynamic Frequency Clocking and multiple voltages for low power designs

In this letter, a scheduling scheme based on Dynamic Frequency Clocking （DFC） and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.     

Design for control-a concurrent engineering approach formechatronic systems design

The well-accepted basis for developing a mechatronic system is a synergetic concurrent design process that integrates different engineering disciplines. In this paper, a general model is derived to mathematically describe the concurrent design of a mechatronic system. Based on this model, a concurrent engineering approach, called design for control (DFC), is formally presented for mechatronic systems design. Compared to other mechatronic design methodologies, DFC emphasizes obtaining a simple dynamic model of the mechanical structure by a judicious structure design and a careful selection of mechanical parameters. Once the simple dynamic model is available, in spite of the complexity of the mechanical structure, the controller design can be facilitated and better control performance can be achieved. Four design scenarios in application of DFC are addressed. A case study is implemented to demonstrate the effectiveness of DFC through the design and control of a programmable four-bar linkage     

Discrete frequency-coded radar signal design

A modified simulated annealing algorithm (MSAA) is proposed as combinatorial multivariable optimisation technique to design discrete frequency-coding (DFC) sequence sets with good auto- and cross-correlation properties. The proposed algorithm is a combination of simulated annealing and Hamming scan algorithm. MSAA has global minimum estimation capability of simulated annealing and fast convergence rate of Hamming scan algorithm. Some of the synthesised results are presented, the properties of the sequence sets are shown to be better than the other sequence sets known in the literature. Synthesised DFC sequence sets have properties far better than polyphase sequence sets. The synthesised DFC sequence sets are promising for practical application to netted radar/multiple radar systems.     

An optical multi-mesh hypercube: a scalable optical interconnectionnetwork for massively parallel computing

A new interconnection network for massively parallel computing is introduced. This network is called an optical multi-mesh hypercube (OMMH) network. The OMMH integrates positive features of both hypercube (small diameter, high connectivity, symmetry, simple control and routing, fault tolerance, etc.) and mesh (constant node degree and scalability) topologies and at the same time circumvents their limitations (e.g., the lack of scalability of hypercubes, and the large diameter of meshes). The OMMH can maintain a constant node degree regardless of the increase in the network size. In addition, the flexibility of the OMMH network makes it well suited for optical implementations. This paper presents the OMMH topology, analyzes its architectural properties and potentials for massively parallel computing, and compares it to the hypercube. Moreover, it also presents a three-dimensional optical design methodology based on free-space optics. The proposed optical implementation has totally space-invariant connection patterns at every node, which enables the OMMH to be highly amenable to optical implementation using simple and efficient large space-bandwidth product space-invariant optical elements     

消除荫罩式等离子体显示器动态伪轮廓方法的研究

由于目前荫罩式等离子体显示器采用ADS驱动时序,产生较明显的动态伪轮廓现象,影响图像的显示质量.本文通过分析动态伪轮廓产生原因,提出了一套通过子场发光积累取代子场发光组合来实现灰度的驱动时序方法.从仿真结果来看,该方法可以消除荫罩式等离子体显示器的动态伪轮廓现象.采用多帧图像的叠加显示和误差扩散方法,很好地解决图像灰度级不足的问题,从而提高荫罩式等离子体显示器的图像质量.     

A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling

A new floating-point division architecture that complies with the IEEE 754-1985 standard is proposed in this paper. This architecture is based on the New Svoboda-Tung (NST) division algorithm and the radix-4 MROR (maximally redundant maximally recoded) signed digit number system. In NST division, the divisor and dividend must be prescaled. We summarize a general systematic method to accomplish the prescaling, and we also propose a hardware scheme such that the timing complexity is constant regardless of the bit length of the divisor. For the divider implementation, a new MROR signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. A 32-b/32-b radix-4 divider is thus designed in Verilog HDL; the simulation results show that this architecture is implementable using currently available libraries. The hardware complexity and performance of this divider is competitive with conventional SRT dividers.     

Limited ride-through capabilities for direct frequency converters

Many solutions to provide continuous operation of adjustable speed drives (ASDs) during power grid disturbances have been proposed, but they are all applied to DC-link ASD. In this paper a new solution to provide limited ride-through operation of a scalar controlled direct frequency converter (DFC) for a duration of hundreds of milliseconds, without any hardware modification, is presented. During the ride-through operation, the drive is not capable of developing torque or to control the motor flux. By recovering the necessary power to feed the control hardware, the DFC is able to keep the ASD operating. When normal grid conditions are re-established, the DFC is also able to accelerate the motor from nonzero speed and flux by initializing the modulator with the estimated frequency and initial voltage vector angle. The duration of the ride-through operation depends on the initial motor flux, speed level, rotor time constant, load torque and inertia     

Dual-mode helical resonators

High performance and compact size are the most important criteria in filter-based products for satellite communication systems. Succeeding the superconducting and dielectric resonators, the conventional single-mode helical resonator ranks favorably on its high unloaded-Q per volume. Improvement of the performance has been demonstrated by operating the helical resonator at a higher order (n>0) mode. In addition, these resonators can also be fabricated onto a high dielectric-constant material to further reduce the size of the filter structure. Detailed design considerations of the dual-mode wire-wound helical resonator filter, as well as implementation of the dual-mode dielectrically loaded helical resonator filter structure, are presented in this paper     

彩色等离子体显示屏中动态假轮廓问题的研究

等离子体显示屏(Plasma Display Panel,PDP)发光在时间上的非线性和人眼平滑跟踪运动目标的自然倾向产生的灰度失调是彩色PDP产生动态假轮廓(Dynamic False Contour,DFC)的主要原因,详细介绍了目前改善DFC的主要方法和基本原理,并对各种方法的优缺点作了分析和评价,提出了一种优化...     

A novel digital FM receiver for mobile and personal communications

A digital baseband receiver called zero-intermediate frequency zero-crossing demodulator (ZIFZCD) was developed for digital FM signal detection. ZIFZCD is applicable to many worldwide mobile and personal communications systems. In addition, ZIFZCD offers lower power consumption and simpler implementation, compared to the conventional analog implementation [e.g., a limiter-discriminator integrator and dump (LDI)] and the conventional digital implementation [e.g., the cross-differentiate-multiply demodulator (CDM)]. This paper introduces the ZIFZCD and reports the bit-error rate (BER) of the ZIFZCD under both static and fading environments. The analyzed and simulated BER results show that the ZIFZCD is comparable to the conventional CDM for narrowband digital FM with a modulation index of 0.5, and the ZIFZCD is significantly better than the CDM for wideband digital FM with a modulation index larger than 1.5