Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.     

A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits

This paper describes a process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage, enables 10% faster performance, 35% reduction in delay variation, and 5/spl times/ reduction in the number of robustness failing dies, compared to conventional designs. A new leakage current sensor design is also presented that can detect leakage variation and generate the keeper control signals for the PCD technique. Results based on measured leakage data show 1.9-10.2/spl times/ higher signal-to-noise ratio (SNR) and reduced sensitivity to supply and p-n skew variations compared to prior leakage sensor designs.     

Microarchitecture-level leakage reduction with data retention

In this paper, we study microarchitecture-level leakage energy reduction by power gating. We consider the virtual power/ground rails clamp (VRC) and multithreshold CMOS (MTCMOS) techniques and apply VRC to memory-based units for data retention and MTCMOS to the other units. We propose a systematic methodology for leakage reduction at the microarchitecture level, in which profiling of idle period distribution and ideal power gating analysis are used to select a target component for realistic power gating. We show that the ideal leakage energy reduction can be up to 30% of the total energy for the modern high-performance very long instruction word processors we study and that the secondary level (L2) cache contributes most to the reduction. We further improve the existing adaptive cache decay method for leakage reduction by using VRC for data retention and name it VRC decay . Applied to L2 cache, the VRC decay, on average, increases performance by 5.6% and reduces system energy by 24.1%, compared to the adaptive cache decay without data retention.     

A leakage reduction methodology for distributed MTCMOS

Multithreshold CMOS (MTCMOS) circuits reduce standby leakage power with low delay overhead. Most MTCMOS designs cut off the power to large blocks of logic using large sleep transistors. Locally distributing sleep devices has remained less popular even though it has several advantages described in this paper. However, locally placed sleep devices are only feasible if sneak leakage currents are prevented. This paper makes two contributions to leakage reduction. First, we examine the causes of sneak leakage paths and propose a design methodology that enables local insertion of sleep devices for sequential and combinational circuits. A set of design rules allows designers to prevent most sneak leakage paths. A fabricated 0.13-/spl mu/m, dual V/sub T/ test chip employs our methodology to implement a low-power FPGA architecture with gate-level sleep FETs and over 8/spl times/ measured standby current reduction. Second, we describe the implementation and benefits of local sleep regions in our design and examine the interfacing issues for this technique. Local sleep regions reduce leakage in unused circuit components at a local level while the surrounding circuits remain active. Measured results show that local sleep regions reduce leakage in active configurable logic blocks (CLBs) on our chip by up to 2.2/spl times/ (measured) based on configuration.     

一种改进的支路漏电流检测方案

直流系统(例如220vdc输出电源系统)支路绝缘下降检测系统中,其使用的漏电流传感器基本都属于闭环式传感器,该传感器有个弊端:一旦现场出现传感器失效的话,更换特别困难。本文提出了一种新的改进方案,具体思路如下:因为高导磁环线圈损坏的概率非常低,绝大部分传感器故障都是其基本电路(运放,方波电路等)的失效导致,采用高导磁环形线圈和基本电路分离措施,把基本电路放置下级采集设备中,万一出现故障,也仅需替换下级采集设备即可,该方案大大减少了支路传感器损坏概率,回避了传感器在线更换困难的难题,与此同时,该改进方案还简化系统接线、降低产品成本。     

Composite-amplifier Wien-bridge oscillator with improved limit-cycle stability

The problem of undesirable low-frequency oscillation which may occur in oscillators with composite amplifiers is discussed. The article shows how the Wien-bridge oscillator proposed by Carlosena et al (1990) should be modified in order to avoid such oscillation and ensure stable operation of the oscillator and good properties of the sinusoidal waveform generated.<>     

Superconducting-cavity stabilized oscillators with improved frequency stability

X-band microwave oscillators stabilized with superconducting niobium cavities with loaded Q's of about 10¹⁰achieved short-term frequency stabilities as low as σy=6 × 10^-16, and typical long-term fractional frequency drifts of ± 2 × 10^-13per day.     

Characterization and modeling of run-time techniques for leakage power reduction

While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and compare three techniques: input vector control, body bias control, and power supply gating. We determine their limits and benefits in terms of the potential leakage reduction, performance penalty, and area and power overhead. The leakage power savings trends considering technology scaling are also presented. Due to the differences in the properties of datapath logic and memory structures, different implementations are recommended. Finally, the use of the "minimum idle time" parameter, as a metric for evaluating different leakage control mechanisms, is shown.     

LECTOR: a technique for leakage reduction in CMOS circuits

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors (a p-type and a n-type) within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this arrangement, one of the LCTs is always "near its cutoff voltage" for any input combination. This increases the resistance of the path from V/sub dd/ to ground, leading to significant decrease in leakage currents. The gate-level netlist of the given circuit is first converted into a static CMOS complex gate implementation and then LCTs are introduced to obtain a leakage-controlled circuit. The significant feature of LECTOR is that it works effectively in both active and idle states of the circuit, resulting in better leakage reduction compared to other techniques. Further, the proposed technique overcomes the limitations posed by other existing methods for leakage reduction. Experimental results indicate an average leakage reduction of 79.4% for MCNC'91 benchmark circuits.     

Gate oxide leakage current analysis and reduction for VLSI circuits

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.     

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.     

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture

A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-/spl mu/m CMOS. This equalized transceiver has been optimized for small area (329 /spl mu/m /spl times/ 395 /spl mu/m) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements.     

Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors

Voltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration.     

Hash routing for collections of shared Web caches

Shared Web caches, also referred to as proxy Web servers, allow multiple clients to quickly access a pool of popular Web pages. An organization that provides shared caching to its Web clients will typically have a collection of shared caches rather than just one. For collections of shared caches, it is desirable to coordinate the caches so that all cached pages in the collection are shared among the organization's clients. In this article we investigate two classes of protocols for coordinating a collection of shared caches: the ICP protocol, which has caches ping each other to locate a cached object; and the hash routing protocols, which place objects in the shared caches as a function of the objects' URLs. Our contribution is twofold. First, we compare the performance of the protocols with respect to cache-server overhead and object retrieval latency; for a collection of shared caches, our analysis shows that the hash-routing schemes have significant performance advantages over ICP for both of the performance metrics. The existing hash-routing protocols assume that the cache servers are homogeneous in storage capacity and processing capability, even though most collections of cache servers are vastly heterogeneous. Our second contribution is to extend a robust hash-routing scheme so that it balances requests among the caches according to any desired distribution; the extended hash-routing scheme is robust in the face of cache failures, is tunable for heterogeneous caches, and can have significant performance advantages over ICP     

A CAM with mixed serial-parallel comparison for use in low energy caches

A novel, low-energy content addressable memory (CAM) structure is presented which achieves an approximately four-fold improvement in energy per access, compared to a standard parallel CAM, when used as tag storage for caches. It exploits the address patterns commonly found in application programs, where testing the four least significant bits of the tag is sufficient to determine over 90% of the tag mismatches; the proposed CAM checks those bits first and evaluates the remainder of the tag only if they match. Although, the energy savings come at the cost of a 25% increase in search time, the proposed CAM organization also supports a parallel operating mode without a speed loss but with reduced energy savings.     

Polarisation-scrambled Er-doped superfluorescent fibre source with improved mean-wavelength stability

A polarisation scrambling scheme is employed to reduce the pump-polarisation-dependent mean-wavelength change in the Er-doped superfluorescent fibre source for gyroscope application. A PZT-based fibre-optic polarisation modulation is used at the pump port for polarisation scrambling. Changes of mean wavelength owing to pump polarisation variation are suppressed below 1 ppm.     

Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports

A proposal to improve the low access bandwidth of conventional one-port caches by utilising a multi-bank structure with distributed crossbar to increase port number at small additional area cost is presented. This enables combination of data and instruction caches into a single multi-port cache as well as different wordlength for each port. Through dynamically scheduling the storage space used for data and instructions, 25% smaller storage capacity is sufficient for a given maximum cache-miss probability.     

一种基于SLM的抑制PAPR的改进算法研究

正交频分复用(OFDM)作为一种特殊的多载波传输(MCM)方案,具有较高的频带利用率和良好的抗多径干扰能力。但较高的峰均功率比(PAPR)是限制其应用的一个主要缺点。选择性映射(SLM)算法是无失真降低OFDM系统PAPR的有效方法,但其复杂度较高。因此提出了一种基于SLM的抑制PAPR的改进算法。仿真结果表明,该方法即有效地降低了SLM实现的复杂度,又大幅降低了PAPR,提高了OFDM系统性能。     

GaInAs n-channel inversion-mode MISFET's with improved long- and short-term stability

CVD SiO2has been used as gate insulator for GaInAs n-channel inversion-mode MISFET's. By applying a rapid thermal annealing cycle with a maximum temperature of 700°C, the number of fast interface states could be strongly reduced, thus leading to stable device performance in the time range between 10^-6and 10 s. The drain current drift for longer times, however, is not affected by the annealing step. A reduction of the dielectric deposition temperature down to 250°C, however, results in improved long-term stability with a drain current decrease of only 5 percent after 10⁴s of operation at room temperature.