共查询到18条相似文献,搜索用时 140 毫秒
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介绍了一款用于分数分频频率综合器的具有量化噪声抑制功能的小数分频器。使用4/4.5双模预分频器,将分频步长降为0.5,使带外相位噪声性能提高6 dB。ΣΔ调制器和分频器的配合使用一种非常简单的编程方式。采用同步电路消除异步分频器的抖动。采用该分频器的频率综合器在SMIC 0.18μm RF工艺下实现,芯片面积为1.47 mm×1 mm。测试结果表明,该频率综合器可以输出1.2~2.1 GHz范围的信号。测试的带内相位噪声小于-97 dBc/Hz,在1 MHz频偏处的带外相位噪声小于-124 dBc/Hz。在1.8 V的电源电压下,消耗的电流为16 mA。 相似文献
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论文介绍了用于散射通信的几种模块化频率综合器方案及相位噪声计算结果,列举了不同频段,不同相位噪声的频率综合器实例及其选择。 相似文献
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本文提出了一个适用于Δ-Σ模数转换器的基于锁相环结构的频率综合器,该频率综合器使用65纳米CMOS工艺实现,频率范围为35-130和300-360兆赫兹。文中提出的频率综合器能够工作在低相位噪声模式和低功耗模式,从而满足系统要求。为了实现这两个模式的切换,片上集成了一个连接4分频器的高频LC压控振荡器和一个连接2分频器的环形压控振荡器。测试结果表明,在1.2伏电源电压下,该频率综合器在低相位噪声模式下消耗1.74毫瓦功耗,1兆频偏处的相位噪声为-132dBc/Hz,标准差周期抖动为1.12皮秒;在低功耗模式下消耗0.92毫瓦功耗,1兆频偏处的相位噪声为-112dBc/Hz,标准差周期抖动为7.23皮秒。 相似文献
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Ku频段卫星通信微波频率综合器 总被引:3,自引:0,他引:3
本文介绍了一种用于卫星通信Ku频段微波频率综合器。首先讨论了该综合器方案设计考虑并对关键技术指标相位噪声进行了简要分析,着重介绍了频率综合器中主要部件的设计制作,最后给出了Ku频段微波频率综合器主要性能指标。 相似文献
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本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断 ΣΔ 调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz~2.1GHz的调谐范围.该频率综合器采用0.18 μ m,1.8V SMIC CMOS工艺实现.SpectreVerilog仿真表明:该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15 μ s的锁定时间. 相似文献
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分析了频率源中各个模块的噪声传递函数,确定影响近端噪声的模块分别是鉴频鉴相器-电荷泵(PFD-CP)、分频器;在默认分频器相位噪声为-158dBc/Hz,通过matlab建模推断,需要PFD-CP模块在10kHz频偏处的输入噪声达到-143dBc/Hz,才能实现频率源输出信号在10kHz频偏处相位噪声-107dBc/Hz。采用0.18μmSiGe BiCMOS工艺,设计了整块芯片,着重优化了PFD-CP模块的输入噪声,经过spectre仿真,PFD-CP模块的输入噪声为-146dBc/Hz,经过实测,输出信号在10kHz频偏处相位噪声为-108dBc/Hz,达到设计预期。 相似文献
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In this paper, an approach of developing high performance millimeter-wave frequency synthesizer is proposed, which is significantly simpler than the conventional cases. The synthesizer is driven by one triple tuned typed synthesizer, which adjusts the output frequency of DDS and frequency division ratios of variable frequency divider to suppress the spurious level. With the proposed method, a microwave phase locked loop (PLL) PE3236 and a millimeter-wave multiplier HMC283 are also used. Moreover, the PLL is implemented with the form of charge pump followed by a passive three-order low-pass filter which can further suppress the phase noise. Finally, a low spurious level and high frequency resolution millimeter-wave frequency synthesizer without degradation of frequency switching speed is developed. Experimental results show that this method can achieve the performances of low spurious level, low phase noise, and high frequency resolution. 相似文献
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A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm2. 相似文献
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小数频率合成技术是实现高分辨率低噪声频率合成器的重要技术手段之一。在分析研究小数频率合成的基本原理及其杂散抑制技术方法上,基于通用灵活的设计思想,采用FPGA集成技术设计了一种基于-Δ调制技术的高性能小数分频器,利用该分频器实现的频率合成器,频率范围800~1 200 MHz,频率分辨率达到nHz量级,偏离主频10 kHz处单边带相位噪声优于-105 dBc/Hz,应用于某高纯微波合成信号发生器中,获得了令人满意的效果。 相似文献
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With the rapid evolution of wireless communication technology,integrating various communication modes in a mobile terminal has become the popular trend.Because of this,multi-standard wireless technology is one of the hot spots in current research.This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications.High-speed divider-by-2 with traditional sourcecoupled-logic is designed for very wide band usage.Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step.The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider.△-Σ modulator is achieved by an improved MASH 1-1-1 structure.This structure has excellent performance in many ways,such as noise,spur and input dynamic range.Fabricated in TSMC 0.18 μm CMOS process,the fractional-N frequency divider occupies a chip area of 1130 × 510μm2 and it can correctly divide within the frequency range of 0.8-9 GHz.With 1.8 V supply voltage,its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA. 相似文献
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针对脉冲无线电超宽频(IR-UWB)接收系统,提出了一种低功耗频率合成器设计。合成器的设计以一个整数N分频II型四阶锁相环结构为基础,包括一个调谐范围为31%的7位压控振荡器,一组基于单相时钟逻辑的高速分频器。分频器能够合成八个由IEEE标准802.15.4a定义的频率。该集成频率合成器运用65 nm CMOS技术制造而成,面积为0.33 mm2,工作频率范围为7.5–10.6 GHz。测试结果显示,在1.2 V供电下,该合成器的3-dB闭环带宽为100 kHz,稳定时间为15 。测量相位噪声低于-103 dBc/Hz@1MHz,抵消频率为1 MHz。杂散信号功率低于低于-58 dBc。相比其他先进的合成器,提出合成器的工作电流为5.13 mA,功耗仅为6.23mW。 相似文献