Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state leakage current is compared experimentally for UTB MOSFETs in two types of materials: 1) strained Si directly on insulator (SSDOI) and 2) strained Si/strained Si/sub 1-z/Ge/sub z/ (z=0.46-0.55)/strained Si heterostructure-on-insulator (HOI). SSDOI of moderate strain level (e.g. /spl sim/ 0.8%) yields high electron-mobility enhancements for all electron densities, while high strain levels (e.g. /spl sim/ 1.6%) are required to obtain hole-mobility enhancements at high inversion charge densities. HOI is demonstrated to have similar electron-mobility characteristics to SSDOI, while hole mobilities are improved and can be maintained at high inversion charge densities. Hole mobility in strained channels with thickness below 10 nm is studied and compared for SSDOI and HOI. As the channel thickness is reduced, mobility decreases, as in unstrained silicon-on-insulator (SOI), though hole-mobility enhancements are demonstrated into the ultrathin-channel regime. Increased OFF-state leakage currents are observed in HOI compared to SSDOI and SOI. For a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels.     

Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body n-MOSFETs With Body Thickness Ranging From 2 to 25 nm

The electron effective mobility in ultrathin-body n-channel metal-oxide-semiconductor field-effect transistors fabricated on Ge-free 30% strained-Si directly on insulator (SSDOI) is mapped as the body thickness is scaled. Effective mobility and device body thickness were extracted using current-voltage and gate-to-channel capacitance-voltage measurements as well as cross-sectional transmission electron microscopy. Devices with body thicknesses ranging from 2 to 25 nm are studied. Significant mobility enhancements ( ~1.8x) compared to unstrained SOI are observed for 30% SSDOI with body thicknesses of above 3.5 nm. The mobility exhibits a sharp drop as the body thickness is scaled below 3.5 nm     

Tradeoff between mobility and subthreshold characteristics in dual-channel heterostructure n- and p-MOSFETs

The mobility and subthreshold characteristics of TiN-gate, dual-channel heterostructure MOSFETs consisting of strained-Si-Si/sub 0.4/Ge/sub 0.6/ on relaxed Si/sub 0.7/Ge/sub 0.3/ are studied for strained-Si cap layer thicknesses ranging from 3 to 10 nm. The thinnest Si cap sample (3 nm) yields the lowest subthreshold swing (80 mV/dec) and the highest hole mobility enhancement (2.3X at a vertical effective field of 1 MV/cm). N-MOSFETs show the expected electron mobility enhancement (1.8X) for 10- and 5-nm-thick Si cap samples, which reduces to 1.6X for an Si cap thickness of 3 nm. For Si cap and gate oxide thicknesses both equal to 1 nm, simulations predict a moderate degradation in p-MOSFET subthreshold swing, from 73 to 85 mV/dec, compared to that for the Si control.     

低温硅结合离子注入技术制备应变Si材料

为制作应变硅MOS器件,给出了一种制备具有高表面质量和超薄SiGe虚拟衬底应变Si材料的方法。通过在Si缓冲层与赝晶Si0.8Ge0.2之间设置低温硅（LT-Si）层,由于失配位错限制在LT-Si层中且抑制线位错穿透到Si0.8Ge0.2层,使表面粗糙度均方根值（RMS）为1.02nm,缺陷密度系106cm-2。又经过P+注入和快速热退火,使Si0.8Ge0.2层的应变弛豫度从85.09%增加到96.41%,且弛豫更加均匀。同时,RMS（1.1nm）改变较小,缺陷密度基本没变。由实验结果可见,采用LT-Si层与离子注入相结合的方法,可以制备出满足高性能器件要求的具有高弛豫度、超薄SiGe虚拟衬底的高质量应变Si材料。     

Growth of strained-Si material using low-temperature Si combined with ion implantation technology

In order to fabricate strained-Si MOSFETs, we present a method to prepare strained-Si material with high-quality surface and ultra-thin SiGe virtual substrate. By sandwiching a low-temperature Si (LT-Si) layer between a Si buffer and a pseudomorphic Si0.08Ge0.2 layer, the surface roughness root mean square (RMS) is 1.02 nm and the defect density is 106 cm-2 owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si0.08Ge0.2 layer. By employing P+ implantation and rapid thermal annealing,the strain relaxation degree of the Si0.08Ge0.2 layer increases from 85.09% to 96.41% and relaxation is more uniform. Meanwhile, the RMS (1.1 nm) varies a little and the defect density varies little. According to the results, the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin SiGe virtual substrate to meet the requirements of device applications.     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.     

Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate

Chemical-mechanical-polishing (CMP) was used to smooth the surface of a SiGe substrate, on which strained-Si n- and p-MOSFETs were fabricated. By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, namely, to 0.4 nm (rms). A strained-Si layer was then successfully grown on the CMP-treated SiGe substrate. The fabricated strained-Si MOSFETs showed good turn-off characteristics, (i.e., equivalent to those of Si control devices). Moreover, capacitance-voltage (CV) measurements revealed that the quality of the gate oxide of the strained-Si devices was the same as that of the Si control devices. Flat-band and threshold voltages of the strained-Si devices were different from those of the Si control devices mainly due to band discontinuity. Electron and hole mobilities of strained-Si MOSFETs under a vertical field up to 1.5 MV/cm increased by 120% and 42%, respectively, compared to the universal mobility. Furthermore, current drive of the n- and p-MOSFETs (L/sub eff//spl ges/0.3 /spl mu/m) was increased roughly by 70% and 50%, respectively. These improvements in characteristics indicate that CMP of the SiGe substrate is a critical technique for developing high-performance strained-Si CMOS.     

Electron mobility enhancement in strained-Si n-MOSFETs fabricatedon SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si_1-xGe_x-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si_0.75Ge_0.26 and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si_1-xGe_x layer     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET’s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor （p-MOSFET） is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si （LT-Si）/10nm S i buffer was grown by Molecular Beam Epitaxy （MBE）, in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET＇s （L=4.2μm） transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm^2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.     

Electron and hole mobility enhancement in strained-Si MOSFET's onSiGe-on-insulator substrates fabricated by SIMOX technology

We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si_0.9Ge_0.1 layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer     

Advanced SOI p-MOSFETs with strained-Si channel onSiGe-on-insulator substrate fabricated by SIMOX technology

We have newly developed an advanced SOI p-MOSFET with strained-Si channel on insulator (strained-SOI) structure fabricated by SIMOX (separation-by-implanted-oxygen) technology. The characteristics of this strained-SOI substrate and electrical properties of strained-SOI MOSFETs have been experimentally studied. Using strained-Si/relaxed-SiGe epitaxy technology and usual SIMOX process, we have successfully formed the layered structure of fully-strained-Si (20 nm)/fully-relaxed-SiGe film (290 nm) on uniform buried oxide layer (85 nm) inside SiGe layer. Good drain current characteristics have been obtained in strained-SOI MOSFETs. It is found that the hole mobility is enhanced in strained-SOI p-MOSFETs, compared to the universal hole mobility in an inversion layer and the mobility of control SOI p-MOSFETs. The enhancement of the drive current has been kept constant down to 0.3 μm of the effective channel length     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

High-mobility strained-Si PMOSFET's

Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si_0.82Ge_0.18 buffer layer on Si(100) substrate. At high vertical fields (high |V_g|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO₂ interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K     

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.     

Scaling and strain dependence of nanoscale strained-Si p-MOSFET performance

Self-consistent fullband Monte Carlo simulations based on nonlocal empirical pseudopotential band structures including spin-orbit splitting are employed to estimate the on-current in nanoscale strained-Si p-MOSFETs. Effective gate lengths from L/sub eff/ = 75 nm down to L/sub eff/ = 25 nm and strain levels corresponding to germanium contents of up to x = 0.4 in the relaxed Si/sub 1-x/Ge/sub x/ substrate are considered. It is found that the on-current continuously increases for growing substrate germanium contents. The strain-induced performance enhancement moderately decreases with scaling, but the improvement at L/sub eff/ = 25 nm still attains 20% for x = 0.4. In contrast to strained-Si n-MOSFETs, increasing the substrate germanium content beyond x = 0.2 is essential for p-MOSFET performance improvement by strain in the sub 0.1 /spl mu/m regime. However, even for x = 0.4 the on-current in a strained-Si p-MOSFET is still smaller than in a corresponding unstrained-Si n-MOSFET.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

The role of carbon on performance of strained-Si:C surface channel NMOSFETs

Carbon incorporation in strained-Si surface channel NMOSFET is investigated. Due to the ～52% lattice mismatch between silicon and carbon, the channel is expected to have higher strain than strained-Si, indicating that the carrier mobility can be enhanced significantly. There is a ～40% electron mobility enhancement for incorporated carbon content of 0.25% in strained-Si NMOSFETs compared to unstrained Si channels. The performance of channels with increased strain is not as high as theoretical predictions. This is due to the large D_it at the oxide/strained-Si:C interface and alloy scattering, which degrades carrier mobility enhancement.     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

Modeling study of the impact of surface roughness on silicon and Germanium UTB MOSFETs

We outlined a simple model to account for the surface roughness (SR)-induced enhanced threshold voltage (V/sub TH/) shifts that were recently observed in ultrathin-body MOSFETs fabricated on <100> Si surface. The phenomena of enhanced V/sub TH/ shifts can be modeled by accounting for the fluctuation of quantization energy in the ultrathin body (UTB) MOSFETs due to SR up to a second-order approximation. Our model is then used to examine the enhanced V/sub TH/ shift phenomena in other novel surface orientations for Si and Ge and its impact on gate workfunction design. We also performed a calculation of the SR-limited hole mobility (/spl mu//sub H,SR/) of p-MOSFETs with an ultrathin Si and Ge active layer thickness, T/sub Body/<10 nm. Calculation of the electronic band structures is done within the effective mass framework via the Luttinger Kohn Hamiltonian, and the mobility is calculated using an isotropic approximation for the relaxation time calculation, while retaining the full anisotropy of the valence subband structure. For both Si and Ge, the dependence of /spl mu//sub H,SR/ on the surface orientation, channel orientation, and T/sub Body/ are explored. It was found that a <110> surface yields the highest /spl mu//sub H,SR/. The increasing quantization mass m/sub z/ for <110> surface renders its /spl mu//sub H,SR/ less susceptible with the decrease of T/sub Body/. In contrast, <100> surface exhibits smallest /spl mu//sub H,SR/ due to its smallest m/sub z/. The SR parameters, i.e. autocorrelation length (L) and root-mean-square (/spl Delta//sub rms/) used in this paper is obtained from the available experimental result of Si<100> UTB MOSFETs, by adjusting these SR parameters to obtain a theoretical fit with experimental data on SR-limited mobility and V/sub TH/ shifts. This set of SR parameters is then employed for all orientations of both Si and Ge devices.