Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure

To investigate the highly boron-doped SiO₂ film, p⁺ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n⁺-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO₂ interface and electrons accumulate near the polysilicon/SiO₂ interface in p⁺-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p⁺ gate's stress time dependence of I_sub is smaller than that of the n⁺ gate, and the electric field near the drain in the p⁺ -gate PMOSFET was found to be more severe than that of the n⁺ -gate device. The subthreshold slope of the p⁺-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n⁺-gated device did not significantly change. The actual change of V_th was larger than the value derived from Δ_gm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO₂ film, which assumes the existence of trapped holes in the p⁺-gate PMOSFET, is proposed to explain these phenomena     

The electron impact ionization rate and breakdown voltage inGaAs/Ga0.7Al0.3As MQW structures

The electron impact ionization rate (α) and breakdown voltage (V_BD) experimentally measured in a p⁺ -i-n⁺ diode structure with a GaAs/Ga_0.7Al _0.3As multiple quantum-well (MQW) i region are discussed. For structures with GaAs wells of 100 Å and barriers that vary from 7 to 60 Å in thickness, it is found that α is always less than α in bulk GaAs and that it decreases with increasing barrier thickness. The normalized V_BD also increases with increasing barrier thickness, confirming a decreasing ionization rate     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

AlGaAs and GaAsP high-power ultrafast p+-n-n+diodes based on heterojunctions and a graded-gap base

The authors present a theoretical model of power p⁺-n-n ⁺ diodes with a graded-gap base and either homojunctions (GB) or heterojunctions (HGB), and numerical calculations of static and dynamic characteristics of AlGaAs (GaAsP) based structures. It is shown that HGB diodes will exhibit characteristics and properties significantly better than those of simple (homojunctions plus uniform base) GaAs and Si diodes. For example, the forward voltage drop in a high-voltage (W/L_p=13) high-frequency (t_rr=25 ns) HGB diode will be 50% and 300% smaller than the drop in, respectively, simple GaAs and Si diodes with the same W/L_p and t_rr. Other significant projected improvements include operation up to 450°C, an order of magnitude reduction in the reverse current, and a 50% increase in the breakdown voltage     

Characteristics of an all-implanted p+-n-n+solar cell

This work presents the main electrooptical parameters of a p⁺-n-n⁺single-crystalline silicon solar cell, whose front p⁺-n junction and the backside n-n⁺contact were fabricated through masked ion implantation of boron (¹¹B+) and phosphorus (³¹p+), respectively. The distinctive feature of the cells consists of the use of the front junction silicon dioxide mask as an AR layer in the finished devices.     

Bulk and surface 1/f noise

The 1/f noise of an n-type silicon MOSFET has been studied under conditions ranging from accumulation to depletion at 300 K. The experimental results are interpreted in terms of a bulk phenomenon and are characterized by Hooge's empirical 1/f noise parameter α with values between 10^-7 and 10^-5. The α value for surface conduction at strong accumulation can be at least one order of magnitude larger than the value for bulk conduction     

A study of residual stress distribution through the thickness of p+ silicon films [thermal oxidation effects]

The effect of thermal oxidation on the residual stress distribution throughout the thickness of heavily-boron-doped (p⁺ ) silicon films is studied. The deflection of p⁺ silicon cantilever beams due to residual stress variation throughout the film thickness is studied for as-diffused and thermally oxidized films. Cantilevers of as-diffused p⁺ silicon films display a positive curvature (or a negative bending moment), signified by bending up of the beams. Thermal oxidation of the films prior to cantilever fabrication by anisotropic etching modifies the residual stresses in the p⁺ film, specially in the near-surface region (i.e. the top 0.3 to 0.5 μm for the oxidation times used here), and can result in beams with a negative curvature even when the oxide is removed from the p⁺ silicon cantilever surface subsequent to cantilever fabrication     

A model of front-illuminated n+-p-p+high-efficiency silicon solar cell

A realistic model of a front-illuminated n⁺-p-p⁺ silicon solar cell is developed by solving the current continuity equations for minority carriers in the quasi-neutral regions in steady state, assuming the light in the cell is trapped as a result of multiple reflections at the front and the back of the cell. This model is used to study the effects of the front emitter thickness and doping level and the light trapping on the J-V characteristic and thereby on the open-circuit voltage, short-circuit current density, curve factor, and the efficiency of the cell. A textured cell with an emitter thickness in the range of 0.3-1.0 μm with its doping ≈5×10¹⁸ cm^-3 and the recombination velocities of minority carriers as large as 200 cm/s at the n⁺ front surface and 10 cm/s at the back of the p base can exhibit an efficiency in excess of 26% (under AM 1.5 sunlight of 100 mW/cm² intensity) at 25°C if the light reflection losses at the front surface can be made small     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

Studies of diffused boron emitters: saturation current, bandgapnarrowing, and surface recombination velocity

The emitter saturation current density, J₀ was measured on diffused boron emitters in silicon for the case in which the emitter surface is passivated by a thermal oxide and for the case in which Al/Si is deposited on the emitter surface. The oxide-passivated emitters have a surface recombination velocity, s, which is near its lowest technologically achievable value. In contrast, the emitters with Al/Si on the surface have surface recombination velocities which approach the maximum possible value of s. From the J ₀ measurements, the apparent bandgap narrowing as a function of boron doping was found. Using this bandgap narrowing data, the surface recombination velocity at the Si/SiO₂ interface was extracted for surface boron concentrations from 3×10¹⁷ to 3×10¹⁹ cm^-3     

A method for the characterization of p+-n-n+diodes using DC measurements

An experimental technique using only dc terminal measurements with a special set of masks is presented for characterizing device properties of single diffused p⁺-n-n⁺diodes. The vertical and lateral current components are separately obtained. The carrier lifetimes in the epitaxial layer and the p⁺diffusion, and the recombination velocity at the oxide-silicon p⁺interface are experimentally determined. Examples are given and possible sources of errors are discussed.     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

pn+ junction in an implanted electroactive polymer:poly(paraphenylene)

The authors have recently shown that specific and stable n or p doping may be obtained on poly(paraphenylene), providing moderate implantation conditions with appropriate ions are used. Here they describe a pn⁺-junction made in intrinsic insulating poly(paraphenylene) (α<10^-12 Ω^-1 cm^-1) by implantation (E≃50 keV) of alkali metal ions (essentially caesium for n doping) and halogen (iodine for p doping)     

Low-temperature growth of silicon-boron layer as solid diffusionsource for polysilicon contacted p+-n shallow junction

A new material, Si-B, is proposed as a solid diffusion source for fabrication of poly-Si contacted p⁺-n shallow junctions. The junction depth of the Si-B source diode has been measured and compared with that of a BF₂⁺-implanted poly-Si source diode. It was found that the Si-B source diode had a much shallower junction and was less sensitive to thermal budget than the BF₂⁺ source diode. This was attributed to the smaller surface concentration and diffusivity of boron in the silicon in Si-B source diodes. Regarding electrical characteristics of diodes with a junction depth over 500 Å, a forward ideality factor of better than 1.01 over 8 decades and a reverse-current density lower than 0.5 nA/cm² at -5 V were obtained. As the junction depth shrank to 300 Å, the ideality factor and reverse current density of diodes increased slightly to 1.05 and 1.16 nA/cm², respectively. These results demonstrated that a uniform ultrashallow p⁺-n junction can be obtained by using a thin Si-B layer as a diffusion source     

Steady-state current through a multilayer homostructure

General analytical formulas are used to describe macroscopic steady-state transport properties in abrupt L-H (n⁺-n, p⁺-p) homostructures as a function of the potential barrier-height reduction. Excellent agreement is found between the theoretical characteristics and previously reported experimental or numerical results. The experiments have been carried out on a family of four Si samples differing only in thickness of the inserted lightly doped layer. An original method for experimental thickness measurements of multilayer structures was employed. The I(V) characteristics have been studied in the steady state and in the pulsed regime (quasi-static). The results establish five bias intervals and three conduction current components. It is shown that the electric properties resulting from a relatively thin multilayer homostructure may be much more sensitive to the geometric factor than to the intrinsic properties of the material composing the inserted layer     

Gain characteristics of ER3+ doped fiber with aquasi-confined structure

The fiber-structure dependence of the gain characteristics of Er ³⁺ doped fibers pumped at 1.48 μm is analyzed. The optimum V value is derived theoretically and experimentally. For step-index fibers, the optimum V value is 1.6, which is smaller than that needed to minimize spot size. The fiber with a small V value enjoys a large Er³⁺ confinement effect. For laser diode pumping, an efficiency of 1.7 dB/mW is achieved at 1.536 μm. The bending characteristics are also described     

A study on the physical mechanism in the recovery of gatecapacitance to Cox in implanted polysilicon MOSstructures

The anomalous CV characteristics of MOS capacitor structures with implanted n⁺ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO₂ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO ₂ gate dielectric should not present a serious problem in device reliability     

A study of the conversion efficiency limit of p+-i-n+silicon solar cells in concentrated sunlight

The conversion efficiency limit of p⁺-i-n⁺silicon solar cells in concentrated sunlight is explored with numerical simulations of an idealized p⁺-i-n⁺cell having field-induced junctions. Conversion efficiencies greater than 30 percent are calculated for this cell operating in sunlight concentrated 1000 times. The relative importance of bulk and surface recombination in limiting the cell conversion efficiency is illustrated for operation in 1 to 1000 suns. For surface recombination velocities below 100 cm/s, it is shown that bulk recombination losses limit the cell performance rather than recombination losses occurring in the p⁺or n⁺regions. The results show that Auger recombination in the bulk region will limit ultimately the cell conversion efficiency.