共查询到20条相似文献,搜索用时 15 毫秒
1.
《Solid-State Circuits, IEEE Journal of》2008,43(11):2413-2421
2.
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2008,55(10):961-965
3.
A digital synchronous mirror delay combined with an analog delay-locked loop (DLL) is introduced. Under the influence of process, voltage, temperature, and load variations, the conventional digital synchronous mirror delay could not compensate the static phase error because of its digital type and open loop by nature. The proposed circuit can compensate the delay mismatch between the output buffer and the inner stage, which is caused by the different loading conditions. It can improve the noise immunity from supply variations. Moreover, because of the tracking property of the DLL, the static phase error and jitter could also be reduced. The proposed circuit has been fabricated by a CMOS 0.35-m one-poly four-metal process and the whole chip area is 1.47 × 1.07 mm2 including I/O pad peripherals. The measured peak-to-peak jitter is 16.4 ps at supply voltage of 3.3 V and frequency of 300 MHz. The power consumption of the entire chip is 16.5 mW for analog part and 84 mW for digital part. The comparisons between the proposed circuit and the conventional digital synchronous mirror delay are also demonstrated. 相似文献
4.
Byung-Guk Kim Lee-Sup Kim 《Solid-State Circuits, IEEE Journal of》2005,40(6):1310-1321
This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DLL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively. 相似文献
5.
Yongsam Moon Jongsang Choi Kyeongho Lee Deog-Kyoon Jeong Min-Kyu Kim 《Solid-State Circuits, IEEE Journal of》2000,35(3):377-384
This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-μm CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm2) and dissipates less power (42 mW) than other wide-range DLL's [2]-[7] 相似文献
6.
Seon-Ho Han Joo-Ho Lee Hoi-Jun Yoo 《Electronics letters》1999,35(20):1700-1701
A fast lock-on time mixed mode delay locked loop (DLL) is proposed to eliminate phase error in two steps. A digital fixed delay line compensates for the initial large phase error and an analogue voltage controlled delay line compensates for the small static phase error, resulting in low jitter. The lock-on time of the DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz 相似文献
7.
Yang Rong-Jyi Liu Shen-Iuan 《Solid-State Circuits, IEEE Journal of》2007,42(11):2338-2347
A 2.5 GHz, 30 mW, 0.03 mm2, all-digital delay-locked loop (ADDLL) in 0.13 mum CMOS technology is presented. The tri-state digital phase detector suppresses the dithering phenomenon and reduces the output peak-to-peak jitter for a counter-controlled digital DLL. The lattice delay unit has both a small delay step and a fixed intrinsic delay of two nand gates. A modified successive approximation register-controller reduces the locking time and allows the DLL to track the process, voltage, temperature, and load variations. This ADDLL locks in 24 cycles and has a closed-loop characteristic. The measured peak-to-peak jitter is 14 ps at 2.5 GHz. 相似文献
8.
《Solid-State Circuits, IEEE Journal of》2009,44(9):2478-2487
9.
This work presents 32-phase analog delay-locked-loop (DLL) having fast locking ability, startup-circuit free operation, and a low area with improved DNL-INL performance. The proposed faster delay-cell and the new bias-circuit enable startup-circuit free operation under process-voltage-temperature (PVT) variation, while the DLL achieves low area and faster locking by using a small filter capacitor. Again, input and output clocks pass through the respective CMOS buffer before the phase detector (PD) for load matching, which reduces DNL-INL in the DLL. The analog DLL locks in less than 54 or 56 clock cycles depending upon initial control voltage (supply or ground voltage) with 100 MHz input clock. The DLL generates 32-phase clocks with a bin-size of 312.5 ps, the peak-to-peak period jitter of 9.51 ps, the rms period jitter of 1.36 ps, the phase-offset error of 4.72 ps, DNL and INL less than ±0.11 LSB. The design consumes 3.54 mW power with a supply voltage of 3.3 V, and an area of 0.017 mm2 in UMC 180 nm MMRF technology. © 2001 Elsevier Science. All rights reserved 相似文献
10.
Hsiang-Hui Chang Shen-Iuan Liu 《Solid-State Circuits, IEEE Journal of》2005,40(3):661-670
An all-digital cycle-controlled delay-locked loop (DLL) is presented to achieve wide range operation, fast lock and process immunity. Utilizing the cycle-controlled delay unit, the proposed DLL reuses the delay units to enlarge the operating frequency range rather than cascade a huge number of delay units. Adopting binary search scheme, the two-step successive-approximation-register (SAR) controller ensures the proposed DLL to lock the input clock within 32 clock cycles regardless of input frequencies. The DLL operates in open-loop fashion once lock occurs in order to achieve low jitter operation with small area and low power dissipation. Since the DLL will not track temperature or supply variations once it is in lock, it is best suited for burst mode operation. Given a supplied reference input with 50% duty cycle, the DLL generates an output clock with the duty cycle of nearly 50% over the entire operating frequency range. Fabricated in a 0.18-/spl mu/m CMOS one-poly six-metal (1P6M) technology, the experimental prototype exhibits a wide locking range from 2 to 700 MHz while consuming a maximum power of 23 mW. When the operating frequency is 700 MHz, the measured peak-to-peak jitter and rms jitter is 17.6 ps and 2.0 ps, respectively. 相似文献
11.
Chao-Chyun Chen Jung-Yu Chang Shen-Iuan Liu 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2007,54(12):1072-1076
A variable-phase clock buffer that uses a delay-locked loop (DLL) is presented. The variable-phase clock is achieved by switching the multiphase outputs of the divider in the DLL. The output phase is adjustable in a step of where pi/n is the ratio of two voltage-controlled delay lines in the proposed circuit. The prototype has been fabricated in a 0.18- CMOS process to realize the output phases of 0deg, 90deg, 180deg, and 270deg. The corresponding measured phase error is 3.24deg, 3.46deg, 3.89deg, and 1.94deg, respectively. The measured root-mean-squared jitter is 1.81 ps. The clock buffer consumes 67 mW including I/O circuits from a single 1.8-V supply at 600 MHz. 相似文献
12.
Garlepp B.W. Donnelly K.S. Jun Kim Chau P.S. Zerbe J.L. Huang C. Tran C.V. Portmann C.L. Stark D. Yiu-Fai Chan Lee T.H. Horowitz M.A. 《Solid-State Circuits, IEEE Journal of》1999,34(5):632-644
A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-μm standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm2 相似文献
13.
《IEEE transactions on circuits and systems. I, Regular papers》2008,55(9):2483-2490
14.
《Solid-State Circuits, IEEE Journal of》2009,44(3):775-783
15.
《Solid-State Circuits, IEEE Journal of》2008,43(9):2079-2089
16.
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(2):117-121
17.
设计并实现了一个基于延时锁定环(DLL)、用于超宽带(UWB)无线通信系统的1.25GHz时钟生成电路。该时钟生成电路由两个DLL和一个自调谐LC滤波电路组成,输入125MHz的参考时钟,输出1.25GHz的差分时钟和间隔100ps的16相时钟。通过优化电荷泵电路有效地减小了静态相位误差,新式自调谐LC滤波电路的应用消除了工艺偏差对谐振的影响。在1.8V电源电压,SMIC0.18μmCMOS工艺下,该时钟生成电路在各种工作条件下均表现出良好的性能,在标准情况下静态相位误差仅为9ps,最大时钟抖动为10ps。当电感存在30%的工艺偏差时,滤波电路的谐振频率能够自动维持在1.25GHz上。 相似文献
18.
19.
《IEEE transactions on circuits and systems. I, Regular papers》2009,56(1):51-59
20.
Seung-Jun Bae Hyung-Joon Chi Young-Soo Sohn Park H.-J. 《Solid-State Circuits, IEEE Journal of》2005,40(5):1119-1129
A dual-loop delay-locked loop (DLL) was implemented by using an analog voltage-controlled delay line (VCDL) for low jitter. An infinite phase-shift capability with seamless phase change was achieved by adding a look-ahead VCDL. A low jitter was achieved for the entire input frequency lock range from 60 to 760 MHz by using the adaptive bandwidth scheme in both reference and fine loops. A wide input-frequency lock range was achieved due to the combined effects of the dual-loop architecture and the extra phase detector of the reference DLL. The extra phase detector eliminated the constraint on the initial VCDL delay for DLL to be locked. Measurements on the fabricated chip by using a 0.18-/spl mu/m CMOS process showed a power consumption of 63 mW at 700 MHz, an active chip area of 370/spl times/510 /spl mu/m/sup 2/, and peak-to-peak jitters of 28 and 39 ps at the 700-MHz synchronous and plesiochronous operations, respectively. 相似文献