Noise parameter modeling for InP-based pseudomorphic HEMTs[InAlAs-InGaAs]

The effect of electron mobility (μ_n) on noise properties for InP-based pseudomorphic HEMTs has been analyzed based on the impedance field model. The analysis predicts that increasing μ _n improves the minimum noise figure (F_min) and associated gain not only because the unity current gain cut-off frequency increases but also because the source resistance is reduced. The analysis also predicts that increasing μ_n reduces the input noise resistance due to higher transconductance but hardly influences the noise-optimum impedance. Furthermore, it is predicted that the decrease in F_min with increasing μ_n becomes less significant above 11000 cm²/Vs due to larger diffusion noise. Calculated results compare well with the measured scattering and noise parameters for In_xGa_1-xAs(x=0.53, 0.7, and 0.8) channel devices. Similar dependence of noise parameters on μ_n is shown in the theoretical and experimental results     

A low-power GaAs front-end IC with current-reuse configurationusing 0.15-μm-gate MODFETs

We have developed a novel current-reuse configuration of a front-end integrated circuit (IC), where the current can be reused in the whole circuit blocks that are a low-noise amplifier, local amplifier, and mixer. The power dissipation of the front-end IC is reduced by the factor of three as compared to conventional front-end ICs. Excellent RF performance such as conversion gain of 30 dB and noise figure of 1.6 dB at 1.5 GHz is attained under the conditions of the supply voltage and current of 3.6 V and 3 mA, respectively     

A 0.5-μm-gate GaAs/AlGaAs inverted HEMT IC-multiplier and D/Aconverter

A gate recess process for a 0.5-μm I-HEMT (inverted high electron mobility transistor) has been developed. A drain conductance for the 0.5-μm I-HEMT as small as 2 mS/mm was achieved, indicating a small short-channel effect. The threshold voltage uniformities were studied in microscopic and macroscopic areas in a 2-in wafer. The uniformities are very high, i.e. the standard deviations of microscopic and macroscopic areas are 10 and 30 mV, respectively, at a threshold voltage of 0.1 V. An 8×4 parallel multiplier was fabricated, and a multiplication time of 1.67 ns was obtained at room temperature. An 8-b digital/analog converter (DAC) was fabricated and operated at a clock rate of 1.2 GHz. The DC linearity of the DAC is better than 0.18 LSB. These results confirm that an I-HEMT is very well suited for high-speed integrated circuits     

Microwave performance of AlInAs-GaInAs HEMTs with 0.2- and0.1-μm gate length

The millimeter-wave performance is reported for Al_0.48In_0.52As-Ga_0.47In_0.53 As high-electron-mobility transistors (HEMTs) with 0.2-μm and 0.1-μm-long gates on material grown by molecular-beam epitaxy on semi-insulating InP substrates. Devices of 50-μm width exhibited extrinsic transconductances of 800 and 1080 mS/mm, respectively. External f_T (maximum frequency of oscillation) of 120 and 135 GHz, respectively, were measured. A maximum f_T of 170 GHz was obtained from a 0.1×200-μm² device. A minimum noise figure of 0.8 dB and associated gain of 8.7 dB were obtained from a single-stage amplifier at frequencies near 63 GHz     

94-GHz 0.1-μm T-gate low-noise pseudomorphic InGaAs HEMTs

Fabrication of state-of-the-art W-band 0.1-μm T-gate pseudomorphic (PM) InGaAs high electron mobility transistors (HEMTs) is reported. This device achieved a noise figure of 2.1 dB with an associated gain of 6.3 dB at 93.5 GHz. The device has a maximum gain of 9.6 dB at 94 GHz, which extrapolates to an F_max of 290 GHz. This noise figure is claimed to be the lowest ever reported for HEMTs fabricated on GaAs substrates at this frequency range     

0.25-μm pseudomorphic HEMTs processed with damage-free dry-etchgate-recess technology

Damage-free, dry-etched 0.25-μm T-shape gate pseudomorphic InGaAs channel HEMTs have been demonstrated. A Freon-12-based discharge was used in either electron cyclotron resonance (ECR) or reactive ion etching (RIE) systems to perform the gate recess process. Etching selectivity of more than 200 was obtained between the GaAs cap layer and the underlying AlGaAs donor layer. Self-bias voltages of -30 to -50 V were used in the etching process to minimize the damage. Pre- and post-etch clean steps were utilized to achieve uniform etch and removal of any dry-etch-related residues. Schottky diodes fabricated on n-GaAs subjected to either dry or wet etching showed no differences of barrier height, zero-bias depletion depth, and ideality factor. By using the dry etch for gate recess, very tight threshold voltage uniformity was obtained. The devices showed I-V characteristics comparable to that of devices fabricated with a wet chemical process     

Very high power-added efficiency and low-noise 0.15-μmgate-length pseudomorphic HEMTs

0.15-μm-gate-length double-heterojunction pseudomorphic high electron mobility transistors (HEMTs) for which excellent millimeter-wave power and noise performance were achieved simultaneously are reported. The 50-μm-wide HEMTs yielded record maximum power-added efficiencies of 51, 41, and 23% at 35, 60, and 94 GHz, respectively. Maximum output powers of 139 mW at 60 GHz and 57 mW at 94 GHz were also measured for 150-μm-gate-width devices. Finally, minimum noise figures as low as 0.55 and 1.8 dB were measured at 18 and 60 GHz respectively. This is the best power and noise performance yet reported for passivated transistors at millimeter-wave frequencies     

High-speed GaAs multipliers fabricated with a high-yield 0.4-μmprocess

A 0.4-μm GaAs IC fabrication process which demonstrates excellent yields for direct-coupled FET logic circuits of up to 5000 gates for high-speed LSI digital applications is discussed. The refractory self-aligned gate process uses 1-μm stepper lithography. An n⁺/n'/buried-p structure results in superior threshold voltage uniformity for a 0.4-μm gate length, with σV _T as low as 8 mV over 3-in wafers. Simple parallel array multipliers were used for process validation. Die-sort yields for a 16-b×16-b multiplier are typically better than 55%, and as high as 88%. A 5000-gate 20-b×20-b multiplier shows yield as high as 61%, and a Poisson yield model predicts a die-sort yield of 30% for a 10000-gate circuit. Multiplication times of 3.6 ns for the 16-b×16-b and 4.5 ns for the 20-b×20-b multiplier have been measured. The corresponding loaded gate delay and power-delay product are 46 ps/gate and 40 fJ, respectively, at room temperature     

DC and microwave characteristics of sub-0.1-μm gate-lengthplanar-doped pseudomorphic HEMTs

Analytical modeling of these very-short-channel HEMTs (high-electron-mobility transistors) using the charge-control model is given. The calculations performed using this model indicate a very high electron velocity in the device channel (3.2±0.2×10⁷ cm/s) and clearly demonstrate the advantages of the planar-doped devices as compared to the conventional uniformly doped HEMTs. Devices with different air-bridged geometries have been fabricated to study the effect of the gate resistance on the sub-0.1-μm HEMT performance. With reduced gate resistance in the air-bridge-drain device, noise figures as low as 0.7 and 1.9 dB were measured at 18 and 60 GHz, respectively. Maximum available gains as high as 13.0 dB at 60 GHz and 9.2 dB at 92 GHz, corresponding to an f_max of 270 GHz, have also been measured in the device. Using the planar-doped pseudomorphic structure with a high gate aspect-ratio design, a noise figure of less than 2.0 dB at 94 GHz is projected based on expected further reduction in the parasitic gate and source resistances     

High performance 3.3- and 5-V 0.5-μm CMOS technology for ASIC's

Process integration of two manufacturable high performance 0.5-μm CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and statistical modeling to reduce circuit performance sensitivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability of the transistors. Manufacturing and simulation data for both 3.3- and 5.0-V technologies will be shown. The nominal ring oscillator delay is measured for both 3.3- and 5.0-V technologies as 80 ps. Therefore, 5.0-V technology equivalent speed is achieved in the 3.3-V technology with a reduction in power consumption by a factor of 2.4     

A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOStechnology

This paper describes the design of a CMOS frequency synthesizer targeting wireless local-area network applications in the 5-GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-μm digital CMOS technology, the circuit provides a channel spacing of 23.5 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBc/Hz at 2.6 GHz and -100 dBc/Hz at 5.2 GHz (both at 10-MHz offset). The reference sidebands are at -53 dBc at 2.6 GHz, and the power dissipation from a 2.6-V supply is 47 mW     

InGaAlAs-InP quantum-well infrared photodetectors for 8-20-μmwavelengths

We demonstrate the first long-wavelength quantum-well infrared photodetectors using the lattice-matched n-doped InGaAlAs-InP materials system. Samples with AlAs mole fractions of 0.0, 0.1, and 0.15 result in cutoff wavelengths of 8.5, 13.3, and 19.4 μm, respectively, a 45° facet coupled illumination responsivity of R=0.37 μm and detectivity of D_λ*=3×10⁸ cm·√(Hz)· at T=77 K, for a cutoff wavelength λ_c=13.3 μm have been achieved. Based on the measured intersubband photoresponse wavelength, a null conduction band offset is expected for In_0.52Ga_0.21Al_0.27 As-InP heterojunctions     

Delay time analysis of submicron InP-based HEMT's

The intrinsic delay time of submicron InP-based HEMT's has been evaluated by coupling the delay time analysis with a 2D Ensemble Monte Carlo Simulation. The relationship between the delay time and the transit time is explained. It is shown that the delay time can be quite different from the transit time depending on the velocity modulation. The delay from each segment of the HEMT is calculated to study the distribution of the delay inside the device. The delay from the gate region was the major contributor while that from the drain region was also important. The bias dependence of the delay in each region of the device was calculated to explain the bias dependence of the total intrinsic delay time. The intrinsic delay time increase at low V_gs was due to the increase of τ_d and τ_s and the increase at high V_ds was due to the increase of τd. As a means of validation, the simulated data have been compared with experimental intrinsic delay time data at various bias points. Good agreement was found over a wide V_gs and V _ds range     

A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

A serial link transmitter fabricated in a large-scale integrated 0.4-μm CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height >350 mV and a width >100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5×2.0 mm² of die area     

Temperature dependent study of the microwave performance of0.25-μm gate GaAs MESFETs and GaAs pseudomorphic HEMTs

We report on the noise figure, associated gain, and the current gain cutoff frequency for comparable 0.25-μm gate GaAs MESFETs and GaAs pseudomorphic HEMTs (p-HEMTs) as a function of cryogenic temperature. Contrary to previously published results which suggest that p-HEMTs should have a higher electron velocity and a lower noise figure than MESFETs due to the effects of the two-dimension electron gas (2-DEG), we have experimentally verified that this is not the case. We show clear evidence that the transport properties of the 2-DEG in p-HEMTs do not make a significant contribution to the speed enhancement and noise reduction during high-frequency operation of these devices. It is the fundamental InGaAs material properties, specifically the Γ-L valley separation in the conduction band and associated effective mass of the electron in either GaAs or InGaAs channel, which limits the high-field electron velocity and thus the speed and noise performance of the devices     

Small-signal analysis of 1.3-μm microcavity light-emittingdiodes

The modulation speed of 1.3-μm microcavity light-emitting diodes (MCLEDs) has been measured using a small-signal modulation analysis. A speed of 260 MHz using a 25-μm diameter sample at current density of 10 kA/cm² has been achieved. The carrier confinement has been calculated for several carrier densities in order to investigate the origin of the speed limitation. By comparing the performance of the 1.3-μm MCLEDs with that of the 990-nm devices we conclude that the limiting factor on the speed seems to be a lack of carrier confinement in the quantum wells and not a cavity effect     

Design and analysis of double-fused 1.55-μm vertical-cavitylasers

Detailed design and experimental characterization of three generations of double-fused vertical-cavity lasers are described. The result of this design evolution is the first above-room-temperature continuous-wave operation of long-wavelength vertical-cavity lasers. Threshold currents of 2.3 mA and yields greater than 90% have been obtained     

1.5-μm-band optical time domain reflectometer for single-modeoptical fiber using a P2O5-highly-doped fiberRaman laser

A wide-dynamic-range 1.5-μm-band optical time-domain reflectometer (OTDR) for single-mode optical fibers using a P₂O₅-highly-doped fiber Raman laser light source and a cooled Ge-p-i-n photodiode is realized for the first time. The stimulated-Raman-scattering properties of P₂O₅-doped single-mode fiber are investigated. Using this fiber and an Nd:YAG laser operating at 1.32 μm, a high-power light pulse at 1.59 μm is generated with high efficiency. Using the stimulated-Raman-scattering light as the light source and a high-sensitivity optical receiver, a 1.5-μm-band OTDR having a one-way dynamic range of 35 dB is realized     

A 0.4-μm gate-length AlGaAs/GaAs P-channel HIGFET with 127-mS/mmtransconductance at 77 K

WN-gate, p-channel AlGaAs-GaAs heterostructure insulated-gate field-effect transistors (HIGFETs) fabricated on a metalorganic vapor-phase epitaxy (MOVPE) wafer are discussed. A self-aligned Mg ion implantation (80 keV, 6×10¹³ cm^-2) annealed at 850°C in an arsine atmosphere and the control of the SiO₂ sidewall dimensions allow the fabrication of p-channel HIGFETs with a gate length smaller than 0.5 μm with low subthreshold current. P-channel HIGFETs with 0.4-μm gate lengths exhibit extrinsic transconductances as high as 127 mS/mm at 77 K and 54 mS/mm at 300 K     

DC to 40 GHz coaxial-to-microstrip transition for 100-μm-thickGaAs substrates

The design, design approach, and test results are presented for a simple coaxial-to-microstrip transition. The approach provides improved performance over the basic coaxial-to-microstrip transition by causing a TEM-to-quasi-TEM transformation through a tapering of the coaxial line for 432±51 μm (≪6% of λ₀ at 40 GHz) prior to impinging a portion of the resultant quasi-TEM field directly across the microstrip's dielectric at the coaxial-microstrip interface. Tests show that the return loss for the transition into a 50-Ω microstrip line on a 100-μm-thick GaAs substrate is better than 16.9 dB per transition from 200 MHz to 40 GHz. A cover having a height of 1.9 mm and a width of 2.6 mm had little or no influence on test results