The development of heterojunction integrated injection logic

The development of heterojunction integrated injection logic (HI ²L) since 1982 is described. The baseline process that uses AlGaAs/GaAs emitter-down HBTs (heterojunction bipolar transistors) as the switching element is presented. Two sets of design rules, one using a 7.0-μm collector and 8.0-μm metal pitch and another using a 5.0-μm collector and 5.0-μm metal pitch, have been developed for the pilot line circuit fabrication. Typical propagation delays obtained for a fan-out=4 HI²L gate using the 7.0- and 5.0-μm collector processes are 250 and 150 ps, respectively, at a power dissipation of 5 mW per gate. LSI and VLSI circuits as complex as 4 K-gate arrays and 32-bit MIPS microprocessors have been fabricated successfully using the HI²L technology     

A 30-ps Josephson current injection logic (CIL)

A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations.     

Shunt-feedback Schottky clamped logic gates

A new approach to digital circuit design is used to develop a new family of TTL-compatible shunt-feedback Schottky clamped logic gates. The virtual ground like input of the shunt-feedback amplifier and the low-impedance input of the familiar diode-biased current source are utilized to perform certain logic and fan-out operations without requiring full logic swings. Voting logic operations as well as conventional Boolean logic operations, such as AND, NAND, OR, NOR, AND-OR, AOI, etc., can all be performed with approximately the same one-gate delay of 2.5 ns. Average dissipation of the NAND gate is 17 mW. The series-terminated transmission-line connection without requiring full logic swing is described.     

A three Josephson junction direct coupled isolation device

A new type of current switching logic device using three Josephson junctions is described. This device allows the simultaneous optimization of both the gain and the operating margin. It shows an enhanced threshold curve compared with that of the Direct Coupled Logic (DCL) isolation device and the Josephson Atto-Weber Switch (JAWS). Design optimization and simulation results are presented. The device shows an almost square current transfer curve indicating good input and output isolation. The dependence of delay on fan-out is also discussed. For a fan-in of 1 and a fan-out of 3, the switching delay is 38 ps with a power dissipation of 3.6 µW.     

Ultra-high-speed digital circuit performance in 0.2-μmgate-length AlInAs/GaInAs HEMT technology

The fabrication of fifteen-stage ring oscillators and static flip-flop frequency dividers with 0.2-μm gate-length AlInAs/GaInAs HEMT technology is described. The fabricated HEMT devices within the circuits demonstrated a g_m transconductance of 750 mS/mm and a full-channel current of 850 mA/mm. The measured cutoff frequency of the device is 120 GHz. The shortest gate delay measured for buffered-FET-logic (BFL) ring oscillators at 300 K was 9.3 ps at 66.7 mW/gate (fan-out=1); fan-out sensitivity was 1.5 ps per fanout. The shortest gate delay measured for capacitively enhanced logic (CEL) ring oscillators at 300 K was 6.0 ps at 23.8 mW/gate (fan-out=1) with a fan-out sensitivity of 2.7 ps per fan-out. The CEL gate delay reduced to less than 5.0 ps with 11.35-mW power dissipation when measured at 77 K. The highest operating frequency for the static dividers was 26.7 GHz at 73.1 mW and 300 K     

氧化锌非线性电阻的特性方程

为了寻找一个能满足工程计算要求的氧化锌非线性电阻的伏安特性方程,对其电阻特性进行了研究,结果发现这种元件的电阻与电流之间有着确定的数量关系,可用"欧安特性方程"来表述。由欧安特性方程推导得到的伏安特性方程能满足工程计算的要求,已成功地应用于新特性产品的开发和浪涌过电压保护设计计算。此外还介绍了非线性电阻器一些特有的物理现象。     

A novel low-power static GaAs MESFET logic gate

A novel GaAs MESFET logic gate is described. The gate uses depletion mode FET's and is a static one. It is about 30% faster and consumes about 30% of the power of the BFL gate. Ring oscillator circuits have been fabricated using one embodiment of the gate. For unity fan-out, an average propagation delay of 58.7 ps with a power dissipation of 18.8 mW has been achieved.     

Demonstration of sub-5 ps CML ring oscillator gate delay withreduced parasitic AlInAs/InGaAs HBT

We have demonstrated a gate delay of 4.9 ps and a power dissipation of 8 mW per CML inverter in an AlInAs-InGaAs HBT technology with 150 mV logic swing. The demonstration circuit was a 15-stage ring oscillator based on CML inverters with a fan-out of 1 and a nominal 3.1 V supply. The same circuit was measured to have a gate delay of 4.7 ps and a power dissipation of 13 mW per inverter using a 3.6 V supply, and a gate delay of 6.2 ps and a power dissipation of 2.4 mW per inverter with a 2.2 V supply. These are the fastest results for a bipolar transistor based logic family in any semiconductor and comparable to the fastest results for any logic family in any semiconductor. Because two gate delays are required for the simplest useful sequential logic circuits such as clocked flip-flops, this is a significant milestone in that it is the first, though somewhat idealized, demonstration that logic at 100 GHz is realizable in InP-based HBT     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

Superintegrated voltage clamp

A monolithic implementation of a voltage clamp circuit is described that saves area and reduces capacitance, as the transistor and the voltage divider resistor required are merged into a single device. Following this principle in current switch logic circuits, even the emitter follower can be superintegrated into the collector loads. Moreover, base-bleeding resistors can be incorporated in transistors of silicon-controlled rectifiers.     

Design of low-power ROM-less direct digital frequency synthesizerusing nonlinear digital-to-analog converter

A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency synthesizer (DDFS) is proposed. The nonlinear DAC is used in place of the ROM look up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. Since the proposed design technique for DDFS does not require a ROM, significant saving in power dissipation results. The design procedure for implementing the nonlinear DAC is presented. To demonstrate the proposed technique, two quadrature DDFSs, one using nonlinear resistor string DACs and the other using nonlinear current-mode DACs, were implemented. For a 3.3-V supply, the resulting power dissipation for both DDFSs are 4 and 92 mW at a clock rate of 25 MHz and 230 MHz, respectively. For both DDFSs, the spurious free dynamic ranges are over 55 dB for low synthesized frequencies     

A compact efficient Schottky collector transistor switch

A vertical Schottky collector transistor switch with merged vertical n-p-n load is described which is useful in both memory and logic applications. The device has been fabricated in an infant oxide isolated bipolar technology with Schottky collector area of 3.8 /spl mu/m/spl times/5.0 /spl mu/m (0.15 mil/spl times/0.2 mil). The intrinsic n-p-n load transistor directly below the Schottky collector requires no additional surface area. Contact location to extrinsic device regions is not restricted, providing wiring flexibility. Current gains of 3 and 4 have been obtained for prototype Schottky collector and n-p-n transistors, respectively. A power-delay product of 60 fJ/V has been observed on a 25-state (fan-out=1) closed-loop inverter chain using 5 /spl mu/m metal lines and spaces. A 5.0 ns delay at 15 /spl mu/A/stage (power-delay product=75 fJ/V) reveals potential for fast, low power VLSI application. The intrinsic speed limit of 2.76 ms is attained at 60 /spl mu/A/stage.     

Modeling and evaluation of positive-feedback source-coupled logic

Positive feedback source-coupled logic (PFSCL) is proposed as an alternative logic style to traditional SCL logic, which is often used in high-resolution mixed-signal integrated circuits. Positive feedback allows for significantly reducing the NMOS transistors' aspect ratio compared to traditional single-ended SCL gates for equal values of design constraints. The resulting reduction in NMOS parasitic capacitances permits a significant speed up, which can be traded off to achieve a power saving for a given speed constraint, as well as a silicon area reduction. PFSCL gates are analytically modeled in terms of their static parameters and delay, which are expressed as a function of bias current, transistors' aspect ratios and process parameters. Spectre simulations by using a 0.35-/spl mu/m CMOS process confirm that the proposed models are sufficiently accurate in practical cases. PFSCL gates are also compared with traditional SCL circuits by resorting to two different metrics: the gate delay in a Ring Oscillator and that of an inverter with a fan-out of 4. The comparison confirms that PFSCL logic is faster than SCL logic in most cases, and design conditions leading to a speed advantage are identified. As a result, PFSCL gates are an interesting alternative to traditional SCL circuits in mixed-signal applications requiring a high speed or a good balance with power dissipation.     

Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

A self-aligned I/sup 2/L/MTL technology featuring collectors doped from and contacted by polysilicon, self-aIigned collector and base contact edges, and metal-interconnected bases is described. Experimental ring-oscillator circuits designed with 2.5-/spl mu/m design roles and fabricated with this technology exhibit gate delays as small as 0.8 ns at lC = 100 -/spl mu/A for fan-in = 1 and fan-out = 3. Increased wiring flexibility and improved circuit density are inherent advantages of this self-aligned technology.     

Subnanosecond self-aligned I2L/MTL circuits

A self-aligned I²L/MTL technology featuring collectors doped from and contacted by polysilicon, self-aligned collector and base contact edges, and metal-interconnected bases is described. Experimental ring-oscillator circuits designed with 2.5-µm design rules and fabricated with this technology exhibit gate delays as small as 0.8 ns atI_{c} = 100µA for fan-in = 1 and fan-out = 3. Increased wiring flexibility and improved circuit density are inherent advantages of this self-aligned technology.     

A comprehensive view of digital integrated electronic circuits

The present generation of digital integrated circuits is based on the batch-fabrication of interconnected transistors and diodes. These circuits successfully provide the elementary logic modules which can be directly interconnected to realize complex digital systems. The basic circuit configurations and their design must fulfill the prime requirement of signal-quantization under various operational aspects; and thus they reflect compromises between the operation speed, the noise margin, the number of fan-in and fan-out, the operating temperature range, the power dissipation, and the cost of fabricating circuit components to the required tolerance.     

Collector diffusion isolated integrated circuits

A new, simplified, bipolar integrated circuit structure is described. This structure eliminates the need for the conventional isolation diffusion. Isolation is accomplished with the collector diffusion. This results in fewer fabrication steps than are required in fabrication of the standard buried collector structure. In addition, the new structure has greater circuit packing density because of the smaller area required for isolation. Transistor-transistor logic circuits have been fabricated using the new structure. Using 5 µm masking tolerances and line widths, propagation delays of 5-7 ns have been obtained at a power dissipation of 4 mW while achieving circuit packing densities 2.5 times higher than obtainable using the standard buried collector structure with the same masking tolerances. Circuits formed using 2-3 µm tolerances and line widths resulted in propagation delays of 20 ns at 0.4 mW power dissipation.     

Schottky collector I/SUP 2/L

A new I/SUP 2/L gate which promises increased packing density and increased speed is discussed. It incorporates the use of a Schottky contact as the collector of the vertical switching transistor of an I/SUP 2/L gate. Calculations and experiments show that the problems associated with this structure (low downward beta) can be controlled by limiting both the fan-out and the fan-in. Delays of less than 10 ns have been measured using a 10-/spl mu/m technology and a 6-/spl mu/m-thick epi. A divide-by-two circuit with a maximum toggle frequency of 12.5 MHz has been built. The additional fan-in limitation of the logic is described.     

Timing-driven logic restructuring for nano-hybrid circuits

As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moore's Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.     

Terminal-oriented model for merged transistor logic (MTL)

A simple device model is derived to represent merged transistor logic (MTL) circuit behavior. Using the Ebers-Moll equations, the proper definitions of the various current gains are derived, and it is shown that MTL devices can be basically interpreted as n-p-n transistors having an additional base current source. The relations between the intensity of this source and the current actually supplied are derived. Time behavior is modeled according to the charge control concept. Using this model, circuit delays are given as a function of current gains, collector and emitter time constants, supply current, and of fan-out.