A novel 8-bit 20-MS/s folded residue amplification based pipelined ADC

A novel circuit is proposed for pipelining of single-slope analog-to-digital converters (ADCs). A new input-to-residue transfer function (TF), called folded residue amplification TF, is proposed for implementing this structure. The proposed structure enables the use of single-slope sub-ADCs in low-power, small-area pipelined structures. The gain of each stage is provided by current mirrors. Based on proposed structure, an 8-bit 20-MS/s fully-differential folded residue amplification based pipelined ADC is designed and simulated in a 90 nm CMOS technology. Calculated ENOB is 7.4-bit with 240 μW power consumption.     

采用前端RC匹配技术的12位40兆赫兹无采样保持的流水线模数转换器

12位40兆赫兹流水线模数转换器采用了前端RC时间常数匹配技术和一组相应的不同占空比时钟时序方法。在不需要繁琐的后端版图仿真验证的情况下,可以很好的提高无采样保持结构流水线模数转换器的线性度。本设计采用0.13微米中芯国际工艺流片实现。通过取消采样保持器技术,运放共享技术和低功耗运放设计来确保低功耗和小面积的设计要求。在40兆赫兹采样时钟和10.2兆赫兹正弦输入信号下,此模数转换器可以达到78.2dB 的无杂散动态范围（SFDR）,60.5dB 的信噪失真比（SNDR）和 -75.5dB 的总谐波失真,在1.2伏的电源电压下,功耗仅为15.6毫瓦。     

A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique

A 12-Bit 40-MS/s pipelined analog-to-digital converter(ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation.Employing SHA-less,opampsharing and low-power opamps for low dissipation and low cost,designed in 0.13-μm CMOS technology,the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range,60.5-dB of signal-to-noise-and -distortion ratio,and -75.5-dB of total harmonic distortion(the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply.     

A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique

A low-voltage opamp-reset switching technique (ORST) that does not use clock boosting, bootstrapping, switched-opamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, the opamps stay active for all clock phases and, therefore, the ORST is suitable for high-speed applications. This new switching technique is applied to the design of a 10-bit 25-MS/s pipelined analog-to-digital converter (ADC). The prototype ADC was fabricated in a 0.35-/spl mu/m CMOS process and demonstrates 55-dB signal-to-noise ratio, 55-dB spurious-free dynamic range, and 48-dB signal-to-noise-plus-distortion ratio performance with a 1.4-V power supply. The total power consumption is 21 mW. The ADC's minimum operating power supply is 1.3 V (|V/sub TH,P/| = 0.9 V) and the maximum operating frequency is 32 MS/s. The ORST is fully compatible with future low-voltage submicron CMOS processes.     

A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

A set of low-power techniques is proposed to realize low power design in pipeline analog-to-digital converter (ADC). These techniques include removing the active S/H (i.e., SHA-less), sharing the opamp between the adjacent multi-bit-per-stages, low-power high-efficiency high-swing amplifier technique. Also, a new sampling topology is proposed to minimize aperture error by matching the time constant between the two input signal paths. All these skills are verified by simulation in the design of the 1.8-V 11-bit 40-MHz ADC in a 0.18-μm CMOS process with power dissipation 21-mW, signal-to-noise-and-distortion ratio (SNDR) 65-dB, effective number of bit (ENOB) 10.5-bit, spurious free dynamic range (SFDR) 78-dB, total harmonic distortion (THD) −75.4-dB, signal-to-noise ratio (SNR) 65.4-dB and figure-of-merit (FOM) 0.18 pJ/step.     

一种有效位为11.3比特的14位100兆CMOS流水线型模数转换器

This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter(ADC) in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio(SNDR) and an 87.5 dB spurious-free dynamic range(SFDR) with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied.     

一种不带校正SFDR为85.2dB的14位100兆流水线模数转换器

This paper describes a 14-bit 100-MS/s calibration-free pipelined analog-to-digital converter （ADC）. Choices for stage resolution as well as circuit topology are carefully considered to obtain high linearity without any calibration algorithm. An adjusted timing diagram with an additional clock phase is proposed to give residue voltage more settling time and minimize its distortion. The ADC employs an LVDS clock input buffer with low-jitter consideration to ensure good performance at high sampling rate. Implemented in a 0.18-μm CMOS technology, the ADC prototype achieves a spurious free dynamic range （SFDR） of 85.2 dB and signal-to-noise-and-distortion ratio （SNDR） of 63.4 dB with a 19.1-MHz input signal, while consuming 412-mW power at 2.0-V supply and occupying an area of 2.9 × 3.7 mm^2.     

一种SFDR为83.5dB的14位100兆流水线模数转换器

This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC）. The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.     

一个不含有传统采样保持放大器的8位100兆采样率流水线模数转换器

本文实现了一个省去传统的采样保持模块的8位100兆采样率流水线模数转换器(ADC)。与包含传统采样保持模块的相同指标的流水线ADC相比,品质因子(FoM)和面积分别降低了21%和12%。提出了一种余量增益放大器(MDAC)中运放的闭环带宽(BWclose)的模型,并通过晶体管级仿真验证了该模型。本设计采用0.18µm 1P6M CMOS混合信号工艺实现,测试结果显示,当采样率为100兆时,输入信号1MHz和80MHz对应的分辨率分别为7.43bit和6.94位,包括内置参考电压/电流源的静态功耗为23.4mW,品质因子为0.85pJ/step,面积为0.53mm2,积分非线性(INL)和差分非线性(DNL)分别为-0.99~0.76LSB,-0.49~0.56LSB。     

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-/spl mu/m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm/sup 2/ of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.     

A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC

A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-μm CMOS.An opampsharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique.The ADC achieves a peak SNDR of 60.1 dB(ENOB = 9.69 bits) and a peak SFDR of 76 dB,while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth.The core area of the ADC is 1.1 mm~2 and the chip consumes 28 mW with a 1.8 V power supply.     

An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

An 8-b 100-MS/s pipelined analog-to-digital converter(ADC) is presented.Without the dedicated sample-and -hold amplifier(SHA),it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,respectively.The closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power optimization.The theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the...     

一种采用开关内置双输入MDAC的10b 80 MS/s 运放共享流水线模数转换器

在0.18-μm CMOS工艺下设计了一种10位80MHz采样频率的运放共享流水线模数转换器,提出了一种开关内置的双输入运放共享的MDAC,从而有效的消除了传统结构存在的无法复位和级间干扰通路的问题。测试结果显示,本设计的模数转换器的SNDR可以达到60.1dB,无杂散动态范围可以达到76dB,有效位为9.69 bit,在整个奈奎斯特带宽内有效位均高于9.6bit。芯片核心面积为1.1 mm2,在1.8 V电源电压下功耗为28mW。     

A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

This paper describes a 10-bit,50-MS/s pipelined A/D converter(ADC) with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier(SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter(MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC(SMDAC) architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pi...     

一种带改进开关和使用新型按比例缩小策略的10位120兆的流水线模数转换器

这篇文章介绍了一种精度为10比特,采样率为120兆的双通道流水线模数转换器(ADC)。这个模数转换器利用了体效应来改善开关的导通性能。在版图绘制中应用了一种新型的按比例缩小的策略。基于0.18μm的CMOS工艺,ADC的整个版图面积为2.05x1.83 mm2。在采样频率为120兆,输入信号频率为4.9兆的情况下,无杂散动态范围达到了74.32dB,信号噪音失真比为55.34dB,3伏供电电压下每通道的功耗为220毫瓦。     

A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling

The residue amplifiers in high-speed pipelined analog-to-digital converters (ADCs) typically determine the converter's overall speed and power performance. We propose a mixed-signal technique that exploits incomplete settling to achieve low power residue amplification. In the first stage of a 12-bit, 75-MS/s proof-of-concept prototype, the employed open-loop residue amplifier dissipates only 2.9 mW from a 3-V supply, achieving >60% amplifier power reduction over a previously reported open-loop residue amplifier implementation and achieving >90% amplifier power reduction over a conventional opamp implementation. Test results show that the converter's maximum signal-to-noise-and-distortion ratio (SNDR) is 65.6 dB. The measured integral and differential nonlinearity are 0.95 LSB and 0.64 LSB, respectively. The experimental chip occupies 7.9 mm² and consumes 273 mW in a 0.35-mum double-poly, quadruple-metal CMOS process     

基于无采样保持和运放共享的10-bit 50-MS/s亚采样流水线模数转换器

摘要：本文采用提出的面积和功耗优化结构,设计了一个10-bit 50-MS/s的流水线模数转换器。本设计将采样保持和第一级转换电路融合为一个模块,既省去了前端采样保持电路,又避免了第一级中余差放大电路和子模数转换器延时路径需要匹配的问题,该模块具有功耗低稳定性高的特点。为了进一步降低面积和功耗,相邻两级间采用运放共享结构,该结构具有运放失调电压和级间串扰影响小的特点。该10-bit模数转换器的实现仅采用了四个运放。测试结果表明,当采样率为50MHz、输入为奈奎斯特频率时,获得52.67dB SFDR和59.44dB SNDR。当输入频率上升到两倍奈奎斯特频率时,该模数转换器仍然保持了稳定的动态性能。本设计采用0.35μm CMOS工艺实现,芯片有效面积仅为1.81mm2,50MHz采样率3.3V供电时功耗为133mW。     

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

This paper presents a prototype analog-to-digital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closed-loop gain errors, closed-loop gain variation, and slew-rate limiting. The prototype consists of an input sample-and-hold amplifier (SHA) that can serve as a calibration queue, a 12-bit 80-MSample/s pipelined ADC, a digital-to-analog converter (DAC) for calibration, and an embedded custom microprocessor, which carries out the calibration algorithm. The calibration is bootstrapped in the sense that the DAC is used to calibrate the ADC, and the ADC is used to calibrate the DAC. With foreground calibration, test results show that the peak differential nonlinearity (DNL) is -0.09 least significant bits (LSB), and the peak integral nonlinearity (INL) is -0.24LSB. Also, the maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 71.0 and 79.6dB with a 40-MHz sinusoidal input, respectively. The prototype occupies 22.6 mm/sup 2/ in a 0.25-/spl mu/m CMOS technology and dissipates 755 mW from a 2.5-V supply.     

A 12-bit 100 MS/s pipelined ADC with digital background calibration

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3×1.6 mm~2, and consumes 205 mW at 1.8 V.