A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture

In this paper, we present a new continuous-time bandpass delta-sigma (/spl Delta//spl Sigma/) modulator architecture with mixer inside the feedback loop. The proposed bandpass /spl Delta//spl Sigma/ modulator is insensitive to time-delay jitter in the digital-to-analog conversion feedback pulse, unlike conventional continuous-time bandpass /spl Delta//spl Sigma/ modulators. The sampling frequency of the proposed /spl Delta//spl Sigma/ modulator can be less than the center frequency of the input narrow-band signal.     

Self-tuning algorithms for high-performance bandpass switched-capacitor /spl Sigma//spl Delta/ modulators

Switched-capacitor high-frequency bandpass /spl Sigma//spl Delta/ modulators could suffer from capacitor mismatch, finite opamp dc gain, and finite opamp bandwidth. These problems make the notch frequency and the quality factor of the zeros of the noise transfer function to deviate from their nominal values, strongly affecting the modulator dynamic range (DR). In order to avoid this situation, two sampled-data algorithms have been developed which allow to self-calibrate the bandpass /spl Sigma//spl Delta/ modulators. They use 3500 gate and 0.043 mm/sup 2/ area and consume power only when they are active, while, when the system is on, they are off and do not interfere with standard operation. The validity of the proposal is demonstrated by a silicon prototype in which the proposed solution allows to guarantee a 75-dB DR performance also under worst case conditions. In the particular case, it allows for the recovery of 3 dB in the SNR for the 200-kHz FM band (from 73 to 76 dB).     

Improved design method for continuous-time quadrature bandpass /spl Sigma//spl Delta/ ADCs

In continuous-time quadrature bandpass /spl Sigma//spl Delta/ ADCs it is desirable to limit the number of cross-couplings. This can be achieved by implementing the loop as a cascade of complex integrators with only real coefficients. It is shown that this may result in a very poor approximation of the desired noise transfer function, because the effect of the DAC pulse is not taken into account correctly. A simple implementation that solves this problem is proposed.     

Interstage network to control overload in cascaded continuous-time /spl Sigma//spl Delta/ modulators

An improved interstage network suitable for avoiding overload and for increasing the signal-to-noise ratio in low-oversampling-ratio cascaded continuous-time SigmaDelta modulators is reported. Feedforward coefficients, going from the input signal to the second stage, are used to control overload without affecting the behaviour of the noise cancellation filters. Moreover, the anti-aliasing functionality is preserved. Simulation results show the utility of the proposed network in terms of the overload performance     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.     

Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

This paper describes an architecture for stable high-order /spl Sigma//spl Delta/ modulation. The architecture is based on a hybrid /spl Sigma//spl Delta/ modulator, wherein hybrid integrators replace conventional analog integrators. The hybrid integrator, which is a combination of an analog integrator and a digital integrator, offers an increased dynamic range and helps make the resulting high-order /spl Sigma//spl Delta/ modulator stable. However, the hybrid /spl Sigma//spl Delta/ modulator relies on precise matching of analog and digital paths. In this paper, a calibration technique to alleviate possible mismatch between analog and digital paths is proposed. The calibration adaptively adjusts the digital integrators so that their transfer functions match the transfer functions of corresponding analog integrators. Through behavioral-level simulations of fourth-order /spl Sigma//spl Delta/ modulators, the calibration technique is verified.     

Hexagonal /spl Sigma//spl Delta/ modulators in power electronics

Design techniques for /spl Sigma//spl Delta/ modulators from communications are applied and adapted to improve the spectral characteristics of high frequency power electronic applications. A high frequency power electronic circuit can be regarded as a quantizer in an interpolative /spl Sigma//spl Delta/ modulator. We review one dimensional /spl Sigma//spl Delta/ modulators and then generalize to the hexagonal sigma-delta modulators that are appropriate to three-phase converters. A range of interpolative modulator designs from communications can then be generalized and applied to power electronic circuits. White noise spectral analysis of sigma-delta modulators is generalized and applied to analyze the designs so that the noise can be shaped to design requirements. Simulation results for an inverter show significant improvements in spectral performance.     

Continuous-time /spl Delta//spl Sigma/ modulators using distributed resonators

We derive a method for using distributed resonators in /spl Delta//spl Sigma/ modulators and demonstrate these /spl Delta//spl Sigma/ modulators have several advantages over existing /spl Delta//spl Sigma/ modulator architectures. Like continuous-time (CT) /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators do not require a high-precision track-and-hold, and additionally can take advantage of the high-Q of distributed resonators. Like discrete-time /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators are relatively insensitive to feedback loop delays and can subsample. We present simulations of several types of these /spl Delta//spl Sigma/ modulators and examine the challenges in their design.     

A continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to interferers

Receivers are being digitized in a quest for flexibility. Analog filters and programmable gain stages are being exchanged for digital processing at the price of a very challenging ADC. This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a /spl Sigma//spl Delta/ ADC. The novel filtering ADC is realized by adding a high-pass feedback path to a conventional /spl Sigma//spl Delta/ ADC while a compensating low-pass filter in the forward path maintains stability. As such, the ADC becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel. As a consequence, the ADC input range can be programmed dynamically to the level of the wanted signal only. This results in an input-referred dynamic range of 89 dB in 1-MHz bandwidth and an intentionally moderate output signal-to-noise-and-distortion ratio of 46-59 dB (depending on the programmed gain). The merged functionality enables a better overall power/performance balance for the receiver baseband. The design consumes less than 2 mW and active area is 0.14 mm/sup 2/ in a 0.18-/spl mu/m digital CMOS technology.     

A 1-V 10.7-MHz fourth-order bandpass /spl Delta//spl Sigma/ modulators using two switched op amps

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-/spl mu/m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.     

Quadrature /spl Sigma//spl Delta/ modulators with a dynamic element matching scheme

This paper presents a new topology of a multibit quadrature bandpass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror image while it reduces the input signal mirror image alias problem to a self-image problem. It is shown that the self-image can be completely removed in switched-capacitor implementations by using the same capacitors to sample the input and the reference of the feedback digital-analog converters (DACs). Moreover, a simple method for extending low-pass mismatch noise shaping techniques to the complex bandpass case is proposed for the case of multibit feedback DACs.     

A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The derivation of the time-interleaved continuous-time /spl Delta//spl Sigma/ modulator from a discrete-time /spl Delta//spl Sigma/ modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass /spl Delta//spl Sigma/ modulator is designed in a 0.18-/spl mu/m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively.     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

This paper presents a high-level synthesis tool for /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time and continuous-time circuit techniques.     

An RC time constant auto-tuning structure for high linearity continuous-time /spl Sigma//spl Delta/ modulators and active filters

An automatic RC time constant tuning scheme is proposed for high linearity continuous-time g/sub m/-C and active RC circuits in a low power consumption environment. Instead of changing the g/sub m/ (in g/sub m/-C filters), the RC time constant is tuned by discretely varying the integration capacitors to preserve a high linearity. The auto-tuning circuit, consisting of an analog integrator, a voltage comparator, and a digital tuning engine, generates a control word and sets on-chip capacitors to obtain an RC time-constant accuracy of /spl plusmn/2-10%. The proposed scheme is verified by the experimental results of a test chip in a 0.5 /spl mu/m CMOS technology. It achieves a peak S/(N+D) of 83 dB while a tuning range of over /spl plusmn/40% is accomplished.     

Noise-coupled /spl Delta//spl Sigma/ ADC's

The first-order noise coupling scheme proposed earlier is generalised to the realisation of higher-order enhancement. It is also extended to single-stage DeltaSigma loops, and to split structures with self-enhancement. The advantages and limitations of these new DeltaSigma architectures are compared with those of conventional single-stage and cascade DeltaSigma structures. As demonstrated by an example, they exhibit improved stability and robustness under practical fabrication conditions     

A fast block-based nonlinear decoding algorithm for /spl Sigma//spl Delta/ modulators

Previous work has established that the digital output of a /spl Sigma//spl Delta/ modulator as an A/D converter contains more information about the analog input than is extracted with conventional linear filtering. Under reasonable mathematical assumptions, optimal nonlinear decoding of the digital output can achieve significantly larger signal-to-noise ratios than linear filtering. However, the hitherto proposed decoding algorithms only demonstrate conceptual feasibility and are impractical from a computational point of view. We present a new block-based decoding algorithm that, like previous work, employs projections onto convex sets. The algorithm owes its speed to a change of projection norm, an accelerated convergence scheme, and a decimation-like subsampling; it is on the order of 10/sup 4/-10/sup 5/ times faster than one previously published algorithm for typical parameter values, and about 2-10 times slower than linear decoding. The new algorithm is applicable to all currently popular /spl Sigma//spl Delta/ architectures.<>     

A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.