Current-voltage characteristics of the junction-gate field-effect transistor with field-dependent mobility

Current-voltage characteristics of the junction-gate field-effect transistor are analyzed based on a depletion layer model of the channel which is divided into subregions of constant mobility and of field-dependent mobility to reproduce the actual situation under various voltage conditions in order to clarify the effect of field-dependent mobility on the characteristics of the device. New formulas for design parameters are given and experimentally verified on specially designed and fabricated samples as well as on commercial samples. Agreement between theory and measurement is good.     

Anomalous noise behavior of the junction-gate field-effect transistor at low temperatures

Measurements are reported on the noise resistance and the noise conductance of the junction-gate FET in the temperature range 77°K-400°K. At low temperatures anomalous noise behavior has been observed. The measurements are discussed in the light of existing theories and, when necessary, the theoretical model has been extended. The agreement is satisfactory. Generally the extra noise is caused by mobility saturation, increased free-carrier temperature, free-carrier trapping and multiplication effects in the pinched-off region. Finally, several applications are discussed in relation to the limiting noise sources.     

Thermal noise in junction-gate field-effect transistors

Measurements are reported on the device parameters and the noise properties of junction-gate field-effect transistors and the results are compared with theory. It is found that the high-frequency input conductance g11and the high-frequency gate-drain conductance g12vary as the square of the frequency and show practically full thermal noise. The high-frequency transconductance decreases with increasing frequency, as expected theoretically. The high-frequency output noise of the FET for short-circuited input is the sum of the low-frequency noise of the FET and the thermal noise of |g12|. A small correlation effect between the short-circuit gate noise and the short-circuit drain noise exists and agrees with theory. An approximate expression for the noise figure is given that is reasonably correct up to the cutoff frequency of the FET.     

High-frequency equivalent circuits of junction-gate field-effect transistors

Series integration of the j.f.e.t. equation makes it possible to obtain a sequence of equivalent circuits of growing complexity and accuracy but of similar structure, valid beyond pinchoff. In particular, a 5-component circuit is proposed which is useful well above the 1/?0 angular frequency (?0 being the transit time in the channel) and, moreover, is readily deduced from the traditional 3-component equivalent circuit.     

Long-channel field-effect transistor with short-channel transistor properties

The typical parameters of samples of long-channel field-effect transistors and the results of measurement of their functional characteristics are presented. The possible distributions of the carrier mobility over the channel thickness are considered. The current-voltage characteristics of long-channel field-effect transistors with an arbitrary doping profile and carrier-mobility gradient are theoretically analyzed taking into account carrier velocity saturation.     

Ambipolar field-effect transistor

The results of measurements performed on an amorphous-silicon thin-film transistor structure are presented and interpreted. The device characteristics show a continuous alternation between n-channel and p-channel operation, an “ambipolar” effect that is made possible by the provision of ohmic source and drain contacts.     

Vacuum-insulated-gate field-effect transistor

A vacuum-insulated-gate field-effect transistor (VIGFET) is fabricated using a modified polysilicon-gate MOS process. The vacuum insulation is formed by first selectively etching the initial SiO/sub 2/ layer under the polysilicon gate in HF and then depositing LPCVD SiO/sub 2/ (LTO) to seal the evacuated cavity under the gate. Initial measurements of n-channel FET drain characteristics result in an effective value for the channel-electron mobility*gate capacitance product of k'= mu /sub n/C'=21 mu A V/sup -2/, comparable to that of conventional MOSFETs.<>     

Theory of low-frequency generation noise in junction-gate field-effect transistors

The theory of the low-frequency generation noise from charge fluctuation of the Shockley-Read-Hall centers in the transition regon of the gate junction of a field-effect transistor is presented. The dominant importance of this mechanism in the transition region compared with other mechanisms in the channel (thermal noise and carrier concentration fluctuation) is shown using a simple one-dimensional model at low frequencies. The two-dimensional analysis of this noise mechanism is then worked out in the gradual channel approximation using both the electrostatic field and the lumped circuit model approaches. Nonideal effects such as surface noise and gate-junction transition region noise outside of the channel are discussed and are found to be negligible compared with this mechanism. It is shown explicitly that the previously published noise theory of the junction-gate field-effect transistors neglects the contribution from this noise source.     

Characteristics of the junction-gate field effect transistor with short channel length

A two-section model of a junction-gate field effect transistor with short channel length was derived. In this model, the current conducting channel is divided into a source and a drain section. The gradual channel approximation with a modification to include the hot electron effect is assumed applicable in the source section. The velocity saturation transport with excess carrier accumulation effect is formulated for the drain section. The normalized design curves and the characteristics of two sample devices are presented.     

V-shaped notched-channel field-effect transistor

A junction field-effect transistor with a V-shaped notched channel fabricated by preferential etching of (100) silicon is described. This transistor exhibits a higher maximum transconductance and a lower turn-on resistance than conventional silicon f.e.t.s. with rectangular channels. The fabrication, characteristics and possible applications of this device are described.     

Vertical tunnel field-effect transistor

The realization of a novel vertically grown tunnel field-effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current-voltage (I/sub D/--V/sub DS/) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temperature independent drain current-gate voltage (I/sub D/--V/sub GS/) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics.     

Dipole heterostructure field-effect transistor

It is proposed to reduce the gate current by using a dipole created by two doped planes, n⁺⁺ and p⁺⁺, in charge control layer, dipole heterostructure field-effect transistors (dipole HFETs) fabricated in AlGaAs/GaAs use doped p⁺⁺ and n ⁺⁺ planes in the charge control AlGaAs layer to form a dipole that provides a considerably larger barrier between the channel and the gate than that in conventional heterostructure FETs. This leads to a reduction of the forward-biased gate current in enhancement-mode n-channel devices, by a factor of approximately 9 at 1.2 V in the experimental devices, when compared with equivalent conventional HFETs. A much broader transconductance region, in the range of 0.5-2.5-V gate bias, a higher maximum drain current, and no negative transconductance are also observed. A comparison between the gate current-voltage characteristics of conventional and dipole HFETs for 1-μm-long and 10-μm-wide gate devices is given. The measured results clearly indicate that a dipole HFET has a much smaller gate leakage current leading to superior performance of enhancement-mode devices. The results demonstrate the effectiveness of the dipole layer concept for digital HFET devices     

A vertical-junction field-effect transistor

A vertical JFET structure is described which allows realization of submicrometer channel-length devices using standard photolithographic techniques. The fabrication procedure utilizes an anisotropic etch followed by an impurity diffusion or implantation to define the channel. A numerical simulation of the JFET operation is implemented using a finite-element analysis technique. Typical devices exhibit high-output conductance and a tendency to resist channel pinchoff at the drain end. Etched bipolar transistors having current gains as high as 400 can also be formed concurrently with the fabrication of the vertical JFET structures.     

The cylindrical field-effect transistor

The characteristics of a cylindrical field-effect transistor are derived analytically on the basis of Shockley's theory of the planar field-effect transistor. It is found that the cylindrical device is capable of giving twice the (voltage) amplification factor of that of the planar device. Its frequency behavior should be comparable to that of the Shockley unit. Because of the loss of one degree of freedom, the transconductance and power characteristics of the cylindrical field-effect transistor are sharply limited. Experimental data support the analytical results.     

Charge-storage junction field-effect transistor

A charge-storage junction FET (CSJFET) has been developed which is capable of storing a charge in its gate region. The storage time can be varied in the orders of several seconds to less than one microsecond by illumination or by hole injection. This function is given by the double-layered structure of the gate region. The stored negative space charge in the floating gate region controls the channel conductance of a CSJFET. An illumination-time convertor and a variable delay-time controller are the basic applications. CSJFET's can easily be fabricated by the bipolar-IC technology.     

Superconductive magnetoelectric field-effect transistor

A transistor-like three-terminal superconducting device-the superconductive magnetoelectric field-effect transistor (SMET)-is described. The SMET represents a field-controlled Josephson device with its control based on the magnetoelectric effect. The device is characterized by a very high input-output isolation because the input is strictly voltage-controlled. As such, it may be useful for interconnecting voltage-controlled semiconductor electronics with current-controlled superconducting devices. The design considerations are reviewed, and preliminary experimental results are presented. Possible other practical applications are also discussed     

Static large-signal field-effect transistor models

A series of static large-signal field-effect transistor (FET) models are presented which consist of familiar circuit building blocks plus a new nonlinear element, the ideal field-effect diode. The models present a unified form for all types of FET's, and generate the complete set of static FET characteristics, including inverted operation.     

Elementary ambipolar field-effect transistor model

An ambipolar FET can be operated alternatively in n-channel and p-channel modes. A simple conceptual model is proposed. It considers ohmic source and drain contacts, a gradual channel, and the depletion approximation.