Testing analog circuits using spectral analysis

In this work a test strategy for analog circuits based on spectral analysis is proposed. The test strategy is blind, in the sense that only statistical information about the input signal is needed, but no sampling of the input signal is required. This feature allows the test of analog circuits with minimum analog hardware addition. In the context of Systems-on-Chip, this strategy needs only the inclusion of a small random signal generator, and transfers most of the signal processing to the digital domain, allowing the use of a purely digital tester or a digital BIST technique. This paper presents the underlying principle of the method and experimental test results for linear analog systems.     

Trimming analog circuits using floating-gate analog MOS memory

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100°C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV     

Simulation techniques for mixed analog/digital circuits

The techniques used in the iSPLICE3 simulator for the analysis of mixed analog/digital circuits are described. iSPLICE3 combines circuit, switch-level timing, and logic simulation modes and uses event driven selective-trace techniques. It also uses a hierarchical schematic capture package called iSPI (Simulation Program Interface) for design entry, circuit partitioning, and simulation control. The contributions here include a new DC solution method, a mixed-mode interface modeling technique, and an automatic partitioning approach for MOS logic circuits. The details of these three methods are provided, along with the architecture and transient simulation algorithms used in iSPLICE3. The results of circuit simulations and mixed-mode simulations of a CMOS static RAM, two A/D converters, and a phase-locked loop are presented. These results indicate that iSPLICE3 is between one and two orders of magnitude faster than SPICE2 with negligible loss in accuracy     

Fault detection in analogue circuits using hybrid evolutionary algorithm and neural network

With the development of analog integrated circuits technology and due to the complexity, and various types of faults that occur in analog integrated circuits, fault detection is a new idea, has been studied in recent decades. In this paper a three amplifier state variable filter is used as circuit under test (CUT) and, a hybrid neural network is proposed for soft fault diagnosis of the CUT. Genetic algorithm (GA) has the powerful ability of searching the global optimal solution, and back propagation (BP) algorithm has the feature of rapid convergence on the local optima. The hybrid of two algorithm will improve the evolving speed of neural network. GA-BP scheme adopts GA to search the optimal combination of weights in the solution space, and then uses BP algorithm to obtain the accurate optimal solution quickly. Experiment results show that the proposed GA-BP scheme is more efficient and effective than BP algorithm.     

Length matching in detailed routing for analog and mixed signal circuits

Heterogeneous integration in modern System-On-Chips (SOCs) drives the design automation process for analog and mixed signal circuit components, where matching constraints for certain analog signals are critical for correct functionality. This paper presents a detailed routing solution for analog nets with the single-layer length matching constraint called LEMAR, i.e., a single-layer LEngth MAtching Router.     

Performance of wavelet analysis and neural networks for pathological voices identification

Within the medical environment, diverse techniques exist to assess the state of the voice of the patient. The inspection technique is inconvenient for a number of reasons, such as its high cost, the duration of the inspection, and above all, the fact that it is an invasive technique. This study focuses on a robust, rapid and accurate system for automatic identification of pathological voices. This system employs non-invasive, non-expensive and fully automated method based on hybrid approach: wavelet transform analysis and neural network classifier. First, we present the results obtained in our previous study while using classic feature parameters. These results allow visual identification of pathological voices. Second, quantified parameters drifting from the wavelet analysis are proposed to characterise the speech sample. On the other hand, a system of multilayer neural networks (MNNs) has been developed which carries out the automatic detection of pathological voices. The developed method was evaluated using voice database composed of recorded voice samples (continuous speech) from normophonic or dysphonic speakers. The dysphonic speakers were patients of a National Hospital ‘RABTA’ of Tunis Tunisia and a University Hospital in Brussels, Belgium. Experimental results indicate a success rate ranging between 75% and 98.61% for discrimination of normal and pathological voices using the proposed parameters and neural network classifier. We also compared the average classification rate based on the MNN, Gaussian mixture model and support vector machines.     

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented     

Pure mode versus mixed mode interfacing between analog circuits

The concepts of transmission error and mismatch factor ^–1 are introduced to evaluate the effect of impedance mismatch on the accuracy of broadband signal transmission between two feedback amplifiers. It is shown that, in comparison with the error introduced by the feedback amplifiers, becomes negligible for pure V.M. (voltage mode) or C.M. (current mode) signal transmission; in the mixed mode, in which a V.M. output circuit feeds a C.M. input circuit, or vice versa, may become significant. Computer simulations show that the pure mode also yields reduced T.H.D., improved bandwidth and improved transient response. It is also shown that a particular combination between the kind of feedback and the active circuit to which it is applied, termed enhancing combination, further increases the accuracy of signal transmission.1. The notation (OL) relates to the open-loop value of the parameter involved.2. It can be shown that rule 2 does not apply to a low-noise preamplifier.     

Satellite image analysis using neural networks

The tremendous backlog of unanalyzed satellite data necessitates the development of improved methods for data cataloging and analysis. Ford Aerospace has developed an image analysis system, Satellite Image Analysis using Neural Networks (SIANN), that integrates the technologies necessary to satisfy NASA's science data analysis requirements for the next generation of satellites. SIANN will enable scientists to train a neural network to recognize image data containing scenes of interest and then rapidly search data archives for all such images. The approach combines conventional image processing technology with recent advances in neural networks to provide improved classification capabilities. SIANN allows users to proceed through a four-step process of image classification: filtering and enhancement, creation of neural network training data via application of feature extraction algorithms, configuring and training a neural network model, and classification of images by application of the trained neural network. A prototype experimentation testbed has been completed and applied to climatological data.     

Evolutionary derivation of optimal test sets for neural network based analog and mixed signal circuits fault diagnosis approach

Testing issues are becoming more and more important with the quick development of both digital and analog circuit industry. In this paper, we study the utilization of evolutionary algorithms for optimal input vectors derivation of neural network based analog and mixed signal circuits fault diagnosis approach and compare the results with normal method. We have introduced a new procedure which uses the n-detection test set concept and selects the input samples in a way that for each case of fault injection, there will be at least n sample to activate that fault. This procedure performs the optimization in two ways. The first one called speed method generates samples in a way that acceptable decision strength and lower training phase duration would be achieved. The second one called stamina method generates samples in a way that best decision strength and higher training phase duration would be achieved. Experimental results demonstrate that the obtained input voltages yields fault diagnosis with increased fault coverage and high decision strength.     

基于分数阶小波的模拟电路参数估计* Deng Yong(邓勇)?, Zhang He(张禾)

Aiming at the problem of parameter estimation in analog circuits, a new approach is proposed. The approach is based on the fractional wavelet to derive the Volterra series model of the circuit under test(CUT). By the gradient search algorithm used in the Volterra model, the unknown parameters in the CUT are estimated and the Volterra model is identified. The simulations show that the parameter estimation results of the proposed method in the paper are better than those of other parameter estimation methods.     

基于组合差异图和卷积小波神经网络的SAR图像变化检测

合成孔径雷达(Synthetic aperture radar,SAR)图像变化检测可以看作是一个分类过程,像素被分类为变化类和不变类.但是,差异图的质量影响了现有方法的检测精度.为了提供高质量的差异图,提出一种基于组合差异图和卷积小波神经网络(Convolutional-Wavelet Neural Network,...     

Smart-pixel cellular neural networks in analog current-mode CMOStechnology

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT's connected in a Darlington structure. Pixel smartness is achieved by exploiting the cellular neural network paradigm, incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-μm technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm², with a power consumption down to 105 μW/unit and image processing times below 2 μs     

Learning capacitive weights in analog CMOS neural networks

Implementations of artificial neural networks as analog VLSI circuits differ in their method of synaptic weight storage (digital weights, analog EEPROMs, or capacitive weights) and in whether learning is performed locally at the synapses or off-chip. In this paper, we explain the principles of analog networks with in situ or local synaptic learning of capacitive weights, with test results of CMOS implementations from our laboratory. Synapses for both simple Hebbian and mean field networks are investigated. Synaptic weights may be refreshed by periodic rehearsal on the training data, which compensates for temperature drift or other nonstationarity. Compact high-performance layouts have been obtained in which learning adjusts for component variability.     

Performance limits of mixed analog/digital circuits with scaledMOSFETs

Constant electric field (CE), quasi-constant voltage (QCV), and constant voltage (CV) scaling laws are used as guides to MOSFET miniaturization. It is found that: 1) the QCV scaling law gives the best performance of the three scaling laws; 2) improvements in unity-gain bandwidth with scaling are less than predicted by the first-order theory due to mobility degradation; 3) gate length can be scaled down to 0.25 μm while maintaining 10-bit accuracy for analog circuits (threshold variation limit); and 4) when gate lengths deviate from designed values, noise immunity for digital circuits is degraded mainly due to degradation in the saturation characteristics (drain-induced barrier lowering)     

模拟电路常见故障的诊断及处理分析

随着科学技术发展日新月异和全民智能化时代的到来,种类繁多的电子产品在人们日常生活中的应用也变得随处可见,从各个方面影响着人们的生活。但是,电子产品在使用过程中也容易受到电路故障的影响而失效。因此,在电子产品电路出现故障时,及时找到故障原因是十分必要的。文章将系统地探寻和分析电路故障的常见诊断方法,达到提升电路故障处理速率的目的,并确保将电路故障带来的损失降至最低。     

Aligned and non-aligned double JPEG detection using convolutional neural networks

Due to the wide diffusion of JPEG coding standard, the image forensic community has devoted significant attention to the development of double JPEG (DJPEG) compression detectors through the years. The ability of detecting whether an image has been compressed twice provides paramount information toward image authenticity assessment. Given the trend recently gained by convolutional neural networks (CNN) in many computer vision tasks, in this paper we propose to use CNNs for aligned and non-aligned double JPEG compression detection. In particular, we explore the capability of CNNs to capture DJPEG artifacts directly from images. Results show that the proposed CNN-based detectors achieve good performance even with small size images (i.e., 64 × 64), outperforming state-of-the-art solutions, especially in the non-aligned case. Besides, good results are also achieved in the commonly-recognized challenging case in which the first quality factor is larger than the second one.     

Salient object detection in video using deep non-local neural networks

Detection of salient objects in image and video is of great importance in many computer vision applications. In spite of the fact that the state of the art in saliency detection for still images has been changed substantially over the last few years, there have been few improvements in video saliency detection. This paper proposes a novel non-local fully convolutional network architecture for capturing global dependencies more efficiently and investigates the use of recently introduced non-local neural networks in video salient object detection. The effect of non-local operations is studied separately on static and dynamic saliency detection in order to exploit both appearance and motion features. A novel deep non-local fully convolutional network architecture is introduced for video salient object detection and tested on two well-known datasets DAVIS and FBMS. The experimental results show that the proposed algorithm outperforms state-of-the-art video saliency detection methods.