DAC动态测试仪

本文介绍了以开环数字高频振荡发生器将ＤＡＣ输出阶梯波的任一部分，在宽带示波器上显示出来的动态测试设备。对ＤＡＣ的差分线性，镇定时间以及开关瞬态幅度等动态指标直观迅速的进行评价。能对几十ＫＨｚ－几十ＭＨｚ，字长１８Ｂｉｔ以内的ＤＡＣ进行测试。     

动态对象的原理、实现与应用

面向对象的思想已被ＣＡＤ、ＥＤＢ等领域普遍接受,本文针对机械ＣＡＤ的需求,提出了动态对象的概念,指出类是对象动态变化中某些状态的抽象,并实现了原型系统ＤＯＣ＋＋（Ｃ＋＋ｗｉｔｈＤｙｎａｍｉｃＯｂｊｅｃｔｓ）。ＤＯＣ＋＋被用来解决产品几何模型的进化问题。     

动态对象的原理,实现与应用

面向对象的思想已被ＣＡＤ、ＥＤＢ等领域普遍接受。本文针对机械ＣＡＤ的需求，提出了动态对象的概念，指出类是对象动态变化中某些状态的抽象，并实现了原型系统ＤＯＣ＋＋（Ｃ＋＋ｗｉｔｈ Ｄｙｎａｍｉｃ Ｏｂｊｅｃｔｓ）．ＤＯＣ＋＋被用来解决产品几何模型的进化问题。     

拇指族社区──铃声自创

摩托罗拉手机曲谱刘德华,谢谢你的爱 节奏＝４ Ｂ１ Ｅ＋２ Ｄ＋２ Ｅ＋２ Ｄ＋２ Ｅ＋２ Ｄ＋１Ｅ＋４ Ｅ＋１ Ｄ＋２Ｂ２　Ｄ＋２　Ｂ１　Ｄ＋４　Ｂ１Ｅ＋２Ｄ＋２Ｅ＋２Ｄ＋１ Ｅ＋２ Ｆ＃＋４ Ｅ＋２ Ｄ＋２ Ｂ２ Ｄ＋２Ｅ＋２ Ｂ４ Ｅ１Ｇ１ Ａ４Ａ２ Ｇ２Ａ１Ｄ＋２Ｂ８黄品源　　你怎么舍得我难过 节奏＝４ Ｆ＋１ Ｆ＋１ Ｆ＋１ Ｅ＋１Ｆ＋２Ｅ＋１Ｅ＋２Ｄ＋１Ｄ＋２ Ｄ＋１Ｃ＋１Ｄ＋１Ｅ＋２Ｅ＋１Ｅ＋２Ｄ＋３Ｃ＋４Ｅ１ Ｃ＋１Ｄ＋１Ｄ＋１Ｄ＋２Ｄ＋２Ａ１Ｃ＋２Ｂ４Ａ１Ｂ１ Ｃ＋２Ｃ＋１Ｃ＋１Ｃ＋２Ｄ＋１Ｅ个４张 宇。…     

16位A/D转换器的精度测试

文中好一种低成本、高可靠性的Ａ．Ｄ转换器（ＡＤＣ）转换精度的计算机辅助测试方法,并对测试系统的原理、结构及算法进行了描述。该方法适合于分率低于１６位的逐次逼近型ＡＤＣ的测试,对ＡＤＣ的入厂检验测试有一定的实用价值。     

安捷伦W-CDMA和cdma 2000发射机测试仪

两种用于ＡｇｉｌｅｎｔＥ４４０６ＡＶＳＡ系列发射机测试仪的测量专用卡能在一台仪器上用一个按键完成对Ｗ -ＣＤＭＡ和ｃｄｍａ２０００制式的测试。利用ＶＳＡ系列测试仪可很容易地进行码功率（ＣＤＰ）测量。该测试仪能自动确定任何代码层的工作信道 ,并以多种速率观察图显示任何码率的ＣＤＰ测量结果。工作信道识别算法简化了未知信号的考察和分析。健全的译码算法允许对发射机进行评估和测试 ,甚至使用加载信号。临近信道功率比（ＡＣＰＲ）测量可以提供大的动态范围 ,并使调整时间减至最短。互补累计分布函数（ＣＣＤＦ）曲线使放大…     

应用细胞化学法与X-射线能谱仪对深低温停循环后脑神经细胞中Ca++浓度的定量研究

用草酸－焦锑酸钾细胞化学法显示深低温（１８℃）停循环（ＤＨＣＡ）１２０ｍｉｎ后脑神经细胞内Ｃａ＋＋的分布及超微结构改变，同时利用Ｘ－射线能谱仪测量细胞内Ｃａ＋＋浓度以及停循环时应用１．６－二磷酸果糖（ＦＤＰ）保护液后细胞内Ｃａ＋＋浓度的变化。结果显示：（ＤＨＣＡ）１２０ｍｉｎ后脑神经细胞超微结构破坏严重，细胞内Ｃａ＋＋浓度明显增加。但在（ＤＨＣＡ）期间应用（ＦＤＰ）脑保护液后可以明显减轻术后神经细胞内Ｃａ＋＋聚积与脑损伤，是（ＤＨＣＡ）下脑保护的可行方法。     

保持系统最佳性能的同时延长电池寿命并且降低功耗的设计难题

远离工作现场的测试系统既要求便携式测试设备高性能工作又要延长电池寿命。此外，数字式超声系 统有２５６～５１２个反射信号通道，每个通道的ＡＤＣ都要求功耗最低的同时保持最佳的动态性能。ＡＤＩ 公司提供的ＡＤＣ可以解决这项设计难题。     

要闻

中国首次第三代移动通信试验系统联合评估顺利完成 本刊讯信息产业部电信科学技术研究院（ＣＡＴＴ）和爱立信公司并协同日本ＤｏＣｏＭｏ公司成功地完成了中国首次第三代移动通信ＷＣＤＭＡ试验系统的联合评估测试工作。测试试验中,该试验系统成功地进行了音频／视频数据、ＵＤＩ和高速分组数据的传输,全部应用和服务都已达到预期数值。４月２４日,三方在电信科学技术研究院召开了评估测试工作的总结报告会。 １９９８年初,ＣＡＴＴ、爱立信和ＮＴＴＤｏＣｏＭｏ公司进行了测试Ｗ—ＣＤＭＡ技术实验系统的可行性研究,并决定尽快进行Ｗ—ＣＤＭＡ实验系统联合测试,目的是了解Ｗ—ＣＤＭＡ技术系统,为Ｗ一ＣＤＭＡ技术的研发、为现有的ＧＳＭ网络平滑地过渡到第三代移动通信做准备。１９９９年６月三方签署了《Ｗ－ＣＤＭＡ技术的联合测试谅解备忘录》,测试工作正式开始。 在９９北京国际无线通信设备展览会上,ＣＡＴＴ、爱立信和ＤｏＣｏＭｏ三家联合进行了Ｗ一ＣＤＭＡ技术的演示。从１９９９年４季度到今年１季度测试项目组进行了实地测试。到今年二季度,Ｗ—ＣＤＭＡ技术实验系统联合测试圆满完成。 此次评估工作是在北京市区进行的。业内人士称,测试工作的顺利完成,为中国平稳地向通...     

应用细胞化学法与X—射线能谱仪对深低温停循环后脑神经细胞中Ca …

用草酸－焦锑酸钾细胞化学法显示深低温（１８℃）停循环（ＤＨＣＡ）在１２０ｍｉｎ后脑神经细胞内Ｃａ＾＋＋的分布及超微结的改变，同时利用Ｘ－射线能谱仪测量细胞内Ｃａ＾＋＋浓度以及停循环时应用１．６－二磷酸果糖（ＦＤＰ）保护液后细胞内Ｃａ＾＋＋浓度的变化，结果显示：（ＤＨＣＡ）１２０ｍｉｎ后脑神经细胞超微结构破坏严重，细胞内Ｃａ＾＋＋浓度明显增加，但在（ＤＨＣＡ）期间应用（ＦＤＰ）脑保护液后可以明业减轻     

A third-order Δ-Σ modulator using second-ordernoise-shaping dynamic element matching

A multibit Δ-Σ modulator is an attractive way of realizing a high-accuracy, high-speed, and low-power data converter. However, the overall resolution of the modulator is determined by the internal digital-to-analog conversion (DAC) linearity. Methods for high-order noise shaping, noise-shaping dynamic element matching (NSDEM), have been proposed in order to overcome this drawback. However, a real implementation has not been realized until now. This paper presents the actual circuit configuration of a tree-structured NSDEM (TNSDEM) technique, which is applied to a multibit Δ-Σ DAC and analog-to-digital converter (ADC) using a nine-level internal DAC. This is the first report of a Δ-Σ ADC and DAC using the second-order NSDEM method. The test chip of the third-order Δ-Σ ADC realizes a signal bandwidth of 100 kHz and a dynamic range of 79 dB in the ADC and 80 dB in the DAC. The test chip only consumes 9.6 mW in the ADC and 5.2 mW in the DAC with a 2.7 V power supply     

基于FPGA的高性能DAC芯片测试与研究

介绍了一种基于现场可编程门阵列（FPGA,field programmable gate array）的高性能数模转换器（DAC,digital to analog converter）性能参数的回路测试方法。以FPGA、DAC和模数转换器（ADC,analog to digital converter）等元器件为硬件测试平台,将待测数字信号转换成模拟信号再转换成数字信号,经过Matlab计算和分析后得到DAC芯片的静态特性参数和动态特性参数。其中失调误差为0.036%,增益误差为3.63%,信号噪声比为58 dB,信号噪声及失真比为57.75 dB,无杂散动态范围为62.84 dB,有效位数为9.3。测试结果表明：测试方法通用性好,精确度高,成本低。     

一种带电流源校准的16bit高性能DAC

设计了一种带电流源校准电路的16 bit高速、高分辨率分段电流舵型数模转换器(DAC)。针对电流舵DAC中传统差分开关的缺点,提出了一种优化的四相开关结构。系统分析了输出电流、积分非线性和无杂散动态范围(SFDR)三个重要性能指标对电流舵DAC的电流源单元设计的影响,完成了电流源单元结构和MOS管尺寸的设计。增加了一种优化设计的电流源校准电路以提高DAC的动态性能。基于0.18μm CMOS工艺完成了该DAC的版图设计和工艺加工,其核心部分芯片面积为2.8 mm^2。测试结果表明,在500 MHz采样速率、100 MHz输入信号频率下,测得该DAC的SFDR和三阶互调失真分别约为76和78 dB,动态性能得到明显提升。     

A novel noise-shaping DAC for multi-bit sigma-delta modulator

This paper describes a new noise-shaping technique for reducing the noise of the internal digital-analog conversion (DAC) in multi-bit low-pass sigma-delta modulators. The proposed technique works with most existing dynamic element matching (DEM) algorithms to provide noise shaping to the DAC noise. The simulation shows that a 10-dB improvement in the signal-to-noise conversion ratio can be obtained with the proposed noise-shaping with DEM (NSDEM) technique. A dithered DAC employing NSDEM is realized in a 0.35-/spl mu/m CMOS process and the test result shows the first-order high-pass noise shaping to the DAC noise, and validates the proposed concept.     

Area-efficient multi-channel active matrix micro-LED driver chip design

This study develops the control and driver for active Micro LED panel with chip-level design. The chip includes constant current circuit, digital-to-analog converter, SPI control interface, and active-matrix display control. The design process uses TSMC0.18um HVG2 CMOS technology, to realize 30 channels for micro LED driver. To reduce I/O pins, the input signals feed to the dynamic shift register in serial, and the results are loaded to the digital-to-analog converter (DAC) in parallel. The DAC module consists of R2R network, unity-gain buffer and sample-and-hold circuits. The DAC outputs with constant current for micro LED driving from voltage-to-current conversion. To reduce the number of DAC component, one DAC can share the common circuit to drive RGB LED of one pixel based on the selected current mirror structure. This chip can greatly reduce resistor and switches about 92% and 96% respectively, compared with the conventional R DAC structure. The measurements result with good linear for the current dimming control, which the test digital signals are generated by Verilog codes to estimate the gray current of this chip.

     

A 10 bit 1 GSPS Nyquist DAC in 180 nm CMOS with high FOM

A new segmented architecture is presented to improve the dynamic and static performance of the current steering digital-to-analog converters (DACs). In the proposed architecture instead of a single binary DAC, distributed binary cells are used. So the effect of the mismatch and timing errors of the binary cells are not accumulated and are averaged out. For realization of the MSB unit cells those binary cells are reused to form the larger weighted unit cells. Realization of the MSB unit cells with smaller cells results in improved dynamic performances as the effects of gradient errors are minimized and the effects of nonlinear parasitic capacitances are reduced. The DAC has been designed in 180 nm five-metal nwell CMOS process. The simulation results show that the DAC can achieve a maximum spurious free dynamic range (SFDR) of 70.99 dB at 2.93 MHz signal for a sampling rate of 1 GSPS considering the mismatch effects. For 1 GSPS sampling rate the simulated Nyquist SFDR is >70 dB with mismatch. The simulated third order intermodulation distortion (IM3) of the DAC with mismatch effect is 71.40 dB, for a dual tone test with 491.21 and 495.12 MHz signals. The DAC is optimized for digital signal synthesis applications in wireless base stations and other communication applications. The power dissipation of the DAC is 78.21 mW at 498.05 MHz signal for a sampling rate of 1 GSPS with 1.8 V supply.     

Pipelined multibit oversampled digital-to-analog converters with capacitor averaging

A combination of pipelined architecture and dynamic element matching technique is applied to multibit oversampled D/A (digital to analog) converters. The approach translates the harmonic distortion components of the nonideal internal DAC (digital-to-analog converter) of the oversampled DAC to high-frequency components, which can then be filtered out by the analog low-pass filter for anti-imaging. Computer simulations have confirmed that with this approach a third-order oversampled DAC employing a 3-bit quantizer, a 3-bit pipelined internal DAC with a random mismatch of 0.1%, can achieve a 94-dB dynamic range with an oversampling ratio of 64 while eliminating the harmonic distortion.This work was supported by NSERC (Canada).     

A self-trimming 14-b 100-MS/s CMOS DAC

A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and dynamic linearity is presented. The DAC is based on a central core of 15 thermometer decoded MSBs, 31 thermometer decoded upper LSBs (ULSBs) and 31 binary decoded lower LSBs (LLSBs). The static linearity corresponding to the 14-b specification is obtained by means of a true background self-trimming circuit which does not use additional current sources to replace the current source being measured during self-trimming. The dynamic linearity of the DAC is enhanced by a special track/attenuate output stage at the DAC output which tracks the DAC current outputs when they have settled but attenuates them for a half-clock cycle after the switching instant. The DAC occupies 3.44 mm×3.44 mm in a 0.35-μm CMOS process, and is functional at up to 200 MS/s, with best dynamic performance obtained at 100 MS/s. At 100 MS/s, power consumption is 180 mW from a 3.3-V power supply, and 210 mW at 200 MS/s     

相位体制数模转换器动态参数的表征与测试

详细分析并讨论了相位体制数模转换器(DAC)动态参数的表征方法,提出用无杂散动态范围(SFDR)、近区谐波失真(TH D 6)、有效工作带宽(EW B)、输出信号功率及正交输出信号幅度一致性来全面描述相位DAC的频域性能。采用上述方法对利用南京电子器件研究所标准76 mm G aA sM ESFET全离子注入工艺流片得到的3b it相位DAC进行了频域测试。结果显示其EW B大于1.5 GH z,转换速率大于12 G bps,全频带内输出信号的正交精度低于4%,幅度一致性低于26%(大多数测试点低于10%)。在500 MH z输入信号下,其SFDR、TH D 6分别为33.8 dB c-、33.7 dB c。该相位DAC的动态参数良好,尤其正交性能优异。     

An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and102-dB DR using a second-order mismatch-shaping DAC

A second-order audio analog-to-digital converter (ADC) ΔΣ modulator using a second-order 33-level tree-structured mismatch-shaping digital-to-analog converter (DAC) is presented. Key logic simplifications in the design of the mismatch-shaping DAC encoder are shown which yield the lowest complexity second-order mismatch-shaping DAC known to the authors. The phenomenon of signal-dependent DAC noise modulation in mismatch-shaping DACs is illustrated, and a modified second-order input-layer switching block is presented which reduces inband DAC noise modulation by 6 dB. Implementation details and measured performance of the 3.3-V 0.5-μm single-poly CMOS prototype are presented. All 12 prototype devices achieve better than 100-dB signal-to-noise-and-distortion and 102-dB dynamic range over a 10-20 kHz measurement bandwidth