Sub-300-ps CBL circuits

Advanced charge-buffered-logic (CBL) circuits featuring double-poly self-alignment, a `free' epi-base lateral p-n-p (cutoff frequency=300 MHz only), and deep trench isolation are discussed. Using 1.2-μm design rules and a modified push-pull output stage, a gate delay (fan-in=3) of 278 ps was obtained at a DC current of 30 μA/gate. The low power-delay product underlies the speed and power potential of CBL as an attractive practical approach to bipolar complementary transistor logic     

Sub-30-ps ECL circuit operation at liquid-nitrogen temperatureusing self-aligned epitaxial SiGe-base bipolar transistors

The authors report the operation of emitter coupled logic (ECL) circuits at liquid-nitrogen temperature using self-aligned epitaxial SiGe-base bipolar transistors. A minimum ECL gate delay of 28.1 ps at 84 K was measured; this is essentially unchanged from the room-temperature value of 28.8 ps at 310 K. This delay number was achieved under full logic-swing (500-mV) conditions and represents an improvement of greater than a factor of 2 over the best reported value for 84 K operation. Lower-power ECL circuits have switching speeds as fast as 51 ps at 2.2 mW (112-fJ power-delay product) at 84 K. These results suggest that silicon-based bipolar technology is suitable for very-high-speed applications in cryogenic computer systems     

Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design andscaling trends

In this paper, we present: 1) design of a single-rail energy-efficient 64-b Han-Carlson ALU, operating at 482 ps in 1.5 V, 0.18-μm bulk CMOS; 2) direct port of this ALU to 0.18-μm partially depleted SOI process; 3) SOI-optimal redesign of the ALU using a novel deep-stack quaternary-tree architecture; 4) margining for max-delay pushout due to reverse body bias in SOI designs; and 5) performance scaling trends of the ALU designs in 0.13-μm generation. We show that a direct port of the Han-Carlson ALU to 0.18-μm SOI offers 14% performance improvement after margining. A redesign of the ALU, using an SOI-favored deep-stack architecture improves the margined speedup to 19%. A 10% margin was required for the SOI designs, to account for reverse body-bias-induced max-delay pushout. Preconditioning the intermediate stack nodes in the dynamic ALU designs reduced this margin to 2%. Scaling the ALUs to 0.13-μm generation reduces the overall SOI speedup for both architectures to 9% and 16%, respectively, confirming the trend that speedup offered by SOI technology decreases with scaling     

XILINX ISL

ISE是Xilinx推出的业内领先的设计工具,提供了极佳的设计性能和生产率组合。ISEDesignSuite整合了Xilinx的嵌入式、DSP和逻辑设计的设计工具。它包含：ISEFoundation软件;ISEWebPACK软件;带有ISE仿真器的ISE Foundation软件;Platform Studio和嵌入式开发套件（EDK）;Plan Ahead设计和分析工具与Plan Ahead Lite;Chip Scope Pro工具;Chip Scope Pro串行I／O工具套件;System Generator for DSP;AccelDSP综合工具。     

Oxide isolated ISL technologies

Using oxide isolation, ISL gates can be fabricated without the relative slow lateral pnp transistor which is inevitable in pn-isolated processes. Now the clamping action is provided either by a fast vertical pnp only, or a reverse operated npn. Using a 1.2 µm thick epilayer and 3 µm minimum dimensions, propagation delay times of 0.7 ns are obtained at a current level of 200 µA per gate.     

Sub-20 ps ECL circuits with high-performance super self-alignedselectively grown SiGe base (SSSB) bipolar transistors

This paper describes a high maximum frequency of oscillation f_max self-aligned SiGe-base bipolar transistor technology, based on a self-aligned selective epitaxial growth (SEG) technology including graded Ge profile in an intrinsic base and link-base engineering using a borosilicate glass (BSG) sidewall structure. The transistor is a new self-aligned transistor, which we call a Super Self-aligned Selectively grown SiGe Base (SSSB) bipolar transistor. The 1st step of the annealing (800°C, 10 min) was performed for the diffusion of boron from the BSG film, before the deposition of an emitter polysilicon film. The 2nd step of the annealing (950°C, 10 sec) of emitter drive-in was carried out, which enabled us to obtain sufficient current gain using in-situ phosphorus doped polysilicon as an emitter electrode. Sheet resistance for a link-region more than one order lower than that of the epitaxial intrinsic base was obtained after heat treatment. Base profile (boron and Ge) design, and the 2-step annealing technique have realized cut-off frequency f_T of 51 GHz and f_max of 50 GHz. ECL circuits of 19-psec gate delay have been achieved     

A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates

A 45 K-gate emitter-coupled-logic (ECL)-compatible array with unbuffered and buffered direct-coupled FET-logic (DCFL and BDCFL) gates has been developed using 0.6-μm-gate high-electron-mobility transistors (HEMTs) and four-level gold-based interconnects. The high-speed DCFL gates and more functional BDCFL gates are used to replace ECL macros efficiently. The basic cell, equivalent to four three-input NOR gates, consists of 12 enhancement-mode (E-mode) HEMTs, four depletion mode (D-mode) HEMTs, and two source-follower buffers. The basic gate delay times are 35 ps for 0.24-mW unbuffered DCFL gates and 50 ps for 0.38-mW BDCFL gates. The gate array chip is 9.8×9.8 mm and contains 45600 gates. The chip dissipates 11 W in 80% gate use. Silylated polymethyl silsequioxane (PMSS), which has a low dielectric constant of 3, is used for the interlayer dielectrics to reduce wiring delay     

43-ps 5.2-GHz macrocell array LSIs

A family of bipolar macrocell array LSIs has been developed which has a basic delay of 43 ps/CML and a toggle frequency of 5.2 GHz/flip-flop. This family uses a cascaded-differential and single-ended CML circuit and a highly advanced super self-aligned process technology (SST-1B) which uses a selectively ion-implanted collector technology based on SST-1A. Using the macrocell array LSIs, performances of 1.2 ns/1.2 W for a 6-bit multiplier, and 4.3 ns/3 W for a 16-bit multiplier have been achieved     

A 150-ps 9000-gate ECL masterslice

A bipolar masterslice chip with an integration level of 9000 gates is described. Internal gate delays down to 150 ps are achieved by utilizing an advanced processiong technology, OXIS III, and a CML circuit technique with three levels of series gating. The 128 mm/SUP 2/ chip has a typical power dissipation of 20 W. I/O levels at 256 logic pins are standard ECL 100 or 10K.     

Propagation delay times of ISL and STL

Propagation delay times of high-speed VLSI candidates ISL and STL are calculated analytically. It is shown by calculations and measurements that STL is marginally faster than ISL in oxide-isolated processes, at the cost of higher process complexity. Both logic forms suffer from speed degradation due to fan-in. Measures to obtain delay times that are independent of fan-in are discussed. Fan-out aspects are also considered. It is shown that ring oscillators exhibit a somewhat better speed than logic gates that start to switch from the DC state. This speed difference is expressed in an empirical formula.     

A sub-nanosec, oxide isolated ISL technology

An oxide isolated Integrated Schottky Logic (ISL) gate has been designed and fabricated using 1.25 µm minimum goemetries and a 1 µm thick epitaxy layer. Computer simulations and experimental results show good agreement and demonstrate that this gate structure provides a room temperative gate delay of approximately 0.7ns at a current level of 100 µA.     

STL versus ISL: an experimental comparison

Schottky-transistor logic (STL) and integrated Schottky logic (ISL) have been fabricated in both 4-/spl mu/m and 2-/spl mu/m oxide isolated processes and characterized over the military temperature range (-55 to +125/spl deg/C ambient). The temperature coefficient of the average propagation delay (t/spl tilde//SUB pd/) is positive for STL over the entire operating current range. For ISL, the temperature coefficient of t/SUB pd/ is negative at low currents and positive at high currents. Both the 4-/spl mu/m and 2-/spl mu/m ring oscillator designs studied showed this behavior. At 25/spl deg/C, t/SUB pd/ data indicate no difference between STL and ISL for practical purposes. At -55/spl deg/C, the STL has a slight (~0.1 ns) speed advantage over ISL. At 150/spl deg/C (junction), the 2-/spl mu/m STL gates with a 200 /spl Omega///spl square/ base sheet resistance have the lowest minimum t/SUB pd/ of the gates studied (0.9 ns at a total current of 190 /spl mu/A) compared to the best for ISL at 1.0 ns and 150 /spl mu/A. The ISL operates at a lower logic swing than the STL at 105/spl deg/C, and has a speed advantage in the current range useful for VLSI. Additional data are presented which demonstrate the effect of the base resistance, epitaxial resistivity and substrate resistivity on delay.     

ISL5216在软件无线电接收机中的应用

首先简要介绍了软件无线电的概念以引出数字下变频器件在软件无线电中的应用。然后对ISL5216的结构与性能进行了说明。接着在一个软件无线电接收机中使用了此款芯片，并说明此接收机的工作流程以及如何实现软件接收控制的．最后以如何实现AM和FM解调为例进行说明，给出了实现解调的原理说明以及如何使用ISL5216配置软件进行设置，以及修改特定寄存器来实现FM解调，且给出了解调后输出的波形以及对应频谱，并对输出结果进行了分析。     

卫星移动通信系统星间链路设计

通过对现有的卫星移动通信系统星间链路的分析发现 ,不但卫星移动通信系统星间链路的指向具有周期性变化的特性 ,而且星间链路的相对距离也在周期性变化。这种星间链路指向的周期性规律变化 ,为星间通信链路的搜索建立以及星间通信设备的设计制造提供了研究的方向和理论依据。对星间链路的误码率的分析 ,主要探讨了由于卫星星体振动而引起的通信误码与振动的标准偏差 (幅度 )、通信所使用的光波波长、发射到接收的距离以及激光波束半径之间的关系 ,为实际星间链路的设计打下了坚实的理论基础。     

30-ps 7.5-GHz GaAs MESFET macrocell array

An ECL-compatible GaAs 250-gate macrocell array has been successfully designed and fabricated using a three-level series gate low-power source-coupled FET logic (LSCFL) and a newly developed 0.4- mu m-gate self-aligned MESFET process. The unloaded propagation delay time was 30 ps/gate at a 2.4-mW/gate power dissipation. The loaded delay time with fan-out=3 and a 2-mm line length was as fast as 74 ps. The flip-flop toggle frequency was 7.5 GHz. A 2*2 asynchronous transfer mode (ATM) switch circuit was constructed on the macrocell array, and a maximum operation frequency of 2 GHz was achieved.<>     

An integrated time-to-digital converter with 30-ps single-shotprecision

A time-to-digital converter (TDC) with 32-ps resolution and 2.5-μs measurement range has been integrated in a 0.8-μm BiCMOS process. The TDC is based on a counter with a 100-MHz clock. Two separate time digitizers improve the time resolution by interpolating within the clock period. These interpolators are based on analog dual-slope conversion. According to test results, the single-shot precision of the TDC is better than 30 ps (σ-value) and the nonlinearity is less than ±5 ps when input time intervals range from 10 ns to 2.5 μs. The conversion time is ⩽6.3 μs. Temperature drift, excluding the temperature dependence of the oscillator, is below ±40 ps in the temperature range of -40 to 60°C. The size of this chip, including pads, is 3.5×3.4 mm² and its power consumption is 350 mW     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

400 dpi integrated contact type linear image sensors with poly-SiTFT's analog readout circuits and dynamic shift registers

Four-hundred-dots-per-inch (dpi) sensors, including poly-Si thin-film-transistor (TFT) scanning circuits, and a-Si photodiodes fabricated on borosilicate glass have been developed. This contact-type image sensor contains TFT analog buffer amplifiers in the readout circuits. The scanning circuits can operate in a frequency range between 200 kHz and 1 MHz. The readout circuits incorporating TFT analog impedance converters decrease photodiode impedance by more than three orders of magnitude and improve the linearity between illumination intensity and the sensor output. High-resolution reading is achieved by the new contact-type linear image sensors with a storage time of 2 ms/line     

Optical ISL tracking considerations in meeting ISDN requirements

Burst errors in an optical intersatellite link (ISL) are short term (of the order of a millisecond) degradations of the link due to antenna mistracking. These errors degrade the average bit error rate (BER), decrease coding gain, complicate calculations of tracking accuracy, and give rise to concern about the quality of the link for carrying digital signals. After reviewing previous work on these topics, the digital performance of the link is examined in terms of how these considerations affect the ability of an optical ISL to meet ISDN (Integrated Services Digital Network) criteria for an ISL. A link with on-board regeneration is assumed. Since no allocation has yet been made for an ISL, an allocation of 25 per cent of the degradation permitted for the satellite link by CCITT Rec. G.821 and CCIR Rec. 614 is assumed here. It is found (1) that if the requirement derived from Rec. 614 is met, the requirements derived from Rec. G.821 are also met and (2) that an optical ISL should have little difficulty in meeting these requirements.